Correlated electron switch structures and applications

Patent metadata

Field	Value
Publication number	US-10937831-B2
Application number	US-201916600372-A
Country	US
Kind code	B2
Filing date	Oct 11, 2019
Priority date	Sep 20, 2016
Publication date	Mar 2, 2021
Grant date	Mar 2, 2021

Abstract

Subject matter disclosed herein may relate to devices formed from correlated electron material.

First claim

What is claimed is:

1. A method comprising:
etching a portion of a metal layer to form a discontinuity between remaining portions of the metal layer;
forming one or more layers of correlated electron material (CEM) over the remaining portions of the metal layer and the discontinuity; and
forming a metal via in the discontinuity over the one or more layers of CEM.

2. The method of claim 1 , and further comprising depositing one or more layers of an electrode material over the remaining portions of the metal layers prior to the forming of the one or more layers of the CEM.

3. The method of claim 2 , wherein the electrode material comprises titanium nitride, platinum, titanium, copper, aluminum, cobalt, nickel, tungsten, tungsten nitride, cobalt silicide, ruthenium oxide, chromium, gold, palladium, indium tin oxide, tantalum, silver or iridium, or any combination thereof.

4. The method of claim 1 , and further comprising depositing one or more layers of an electrode material over the remaining portions of the metal layers prior to the forming of the one or more layers of the CEM.

5. The method of claim 1 , wherein forming the one or more layers of correlated electron material (CEM) over the remaining portions of the metal layer and the discontinuity further comprises depositing the one or more layers.

6. The method of claim 1 , wherein forming the one or more layers of CEM over the remaining portions of the metal layer and the discontinuity comprises forming at least one layer of CEM to provide at least one continuous switching region and forming at least two of the layers of CEM to provide at least two conductive regions.

7. The method of claim 1 , wherein forming the one or more layers of CEM over the remaining portions of the metal layer and the discontinuity further comprises forming the one or more layers of CEM to comprise two or more discontinuous switching regions and at least two conductive regions.

8. The method of claim 7 , and further comprising forming the two or more discontinuous switching regions to comprise intrinsic CEM and forming the two or more conductive regions to comprise p-type doped CEM.

9. The method of claim 7 , and further comprising forming the two or more discontinuous switching regions to comprise p-type doped CEM and forming the two or more conductive regions to comprise intrinsic CEM.

10. A device comprising:
a substrate;
metal layer formed on the substrate, the metal layer to comprise at least one discontinuity;
one or more layers of correlated electron material (CEM) to be formed in the discontinuity; and
a metal via to be formed in the discontinuity.

11. The device of claim 10 , wherein the one or more layers of CEM to comprise at least one layer of CEM to form a switching region, and two or more layers of CEM to form two or more conductive regions.

12. The device of claim 10 , wherein the switching region to comprise intrinsic CEM and the two or more conductive regions to comprise p-type doped CEM.

13. The device of claim 11 , wherein the switching region to comprise p-type doped CEM and the two or more conductive regions to comprise intrinsic CEM.

14. The device of claim 10 , and further comprising one or more layers of electrode material formed between the metal via and the one or more layers of CEM.

15. The device of claim 10 , and further comprising one or more layers of an electrode material disposed between at least a portion of the one or more layers of CEM and the substrate.

16. The device of claim 15 , wherein the electrode material to comprise titanium nitride, platinum, titanium, copper, aluminum, cobalt, nickel, tungsten, tungsten nitride, cobalt silicide, ruthenium oxide, chromium, gold, palladium, indium tin oxide, tantalum, silver or iridium, or any combination thereof.

17. The device of claim 10 , wherein the switching region to comprise a continuous switching region and at least two of the one or more layers to comprise at least two conductive regions.

18. The device of claim 10 , wherein the one or more layers of CEM to comprise two or more discontinuous switching regions, and at least two of the one or more layers to comprise at least two conductive regions.

19. The device of claim 18 , wherein the two or more discontinuous switching regions to comprise intrinsic CEM and the two or more conductive regions to comprise p-type doped CEM.

20. The device of claim 18 , wherein the two or more discontinuous switching regions comprise p-type doped CEM and the two or more conductive regions to comprise intrinsic CEM.

Assignees

• Advanced Risc Mach Ltd
• Cerfe Labs Inc

Inventors

• Shifren Lucian
• Reid Kimberly Gay
• Yeric Gregory Munson

Classifications

• H10N70/063 Primary

  by etching of pre-deposited switching material layers, e.g. lithography · CPC title

• H10N70/028

  by conversion of electrode material, e.g. oxidation · CPC title

• H10B63/30 Primary

  comprising selection components having three or more electrodes, e.g. transistors · CPC title

• H10N70/8833

  Binary metal oxides, e.g. TaOx · CPC title

• H10N70/826

  adapted for essentially vertical current flow, e.g. sandwich or pillar type devices · CPC title