Interleaved inverter

Patent metadata

Field	Value
Publication number	US-11677331-B2
Application number	US-202217580223-A
Country	US
Kind code	B2
Filing date	Jan 20, 2022
Priority date	Dec 12, 2019
Publication date	Jun 13, 2023
Grant date	Jun 13, 2023

Abstract

A system and method for an interleaved inverter including a set of module circuits and an inverter controller. The module circuits include multiple switches. The inverter controller is configured to assign a first phase shift value to each of the module circuits during a normal mode of operation and assign a second phase shift value to at least one of the module circuits during a failure mode of operation. The second phase shift value is greater than the first phase shift value.

First claim

We claim:

1. An interleaved inverter comprising:
a plurality of module circuits including a plurality of switches; and
an inverter controller configured to operate the plurality of module circuits in a normal mode of operation and a failure mode of operation,
wherein at least one of the plurality of module circuits operates at a first power level during the normal mode of operation and a second power level during the failure mode of operation,
wherein the second power level is greater than the first power level.

2. The interleaved inverter of claim 1 , further comprising:
an electrical isolator coupled between a direct current (DC) bus and at least one of the plurality of module circuits, wherein the electrical isolator is configured to disconnect the at least one of the plurality of module circuits.

3. The interleaved inverter of claim 1 , further comprising:
a common filter element coupled to each of the plurality of module circuits and configured to reduce electrical ripple output from the module circuit.

4. The interleaved inverter of claim 3 , wherein the common filter element includes a common capacitor electrically coupled to each of the plurality of module circuits.

5. The interleaved inverter of claim 4 , wherein the common filter element is a direct current (DC) Link capacitor for a DC bus or an alternating current (AC) output capacitor.

6. The interleaved inverter of claim 3 , further comprising:
a module filter element for each of the plurality of module circuits coupled to a first terminal of the common filter element.

7. The interleaved inverter of claim 1 , wherein the controller is configured to select a timing control for the plurality of switches in response to the normal mode of operation and the failure mode of operation.

8. The interleaved inverter of claim 1 , further comprising:
a sensor configured to generate sensor data for an electrical parameter of at least one of the plurality of module circuits, wherein the controller is configured to receive the sensor data and detect a failure or a disconnection of at least one of the plurality of module circuits.

9. The interleaved inverter of claim 8 , wherein the controller is configured to disconnect the at least one of the plurality of module circuits in response to the detected failure.

10. The interleaved inverter of claim 8 , wherein the second phase shift value is assigned to the other module circuits of the plurality of module circuit in correspondence with the disconnection of the at least one of the plurality of module circuits.

11. The interleaved inverter of claim 1 , wherein the controller selects a sacrificial module circuit in response to an external overload condition and operates the sacrificial module circuit to decrease a probability of failure in the plurality of module circuits other than the sacrificial module circuit in response to the external overload condition.

12. The interleaved inverter of claim 1 , wherein the controller provides a module circuit replacement message for the failure mode of operation while the plurality of module circuits other than the disconnected module circuit continue to operate.

13. The interleaved inverter of claim 1 , wherein the inverter controller is configured to calculate a first peak efficiency power rating for the normal mode of operation and a second peak efficiency power rating for the failure mode of operation.

14. The interleaved inverter of claim 1 , wherein the inverter controller is configured to calculate a first estimated total harmonic distortion value for the normal mode of operation and a second estimated total harmonic distortion value for the failure mode of operation.

15. The interleaved inverter of claim 1 , wherein the inverter controller is configured to generate, in response to the failure mode of operation, a module command to adjust a switching frequency for at least one of the plurality of switches, a load shed command to connect or disconnect a load connected to the plurality of module circuits, or an output level for at least one of the plurality of module circuit.

16. The interleaved inverter of claim 1 , wherein the inverter controller is configured to generate a first pulse width modulation signal for the normal mode of operation and a second pulse width modulation signal for the failure mode of operation.

17. A method for operation of an interleaved inverter, the method comprising:
selecting a normal mode of operation for a plurality of module circuits including a plurality of switches;
receiving sensor data indicative of a failure of one of the plurality of module circuits; and
selecting a failure mode of operation for the plurality of module circuits in response to the sensor data,
wherein at least one of the plurality of module circuits operates at a first power level during the normal mode of operation and a second power level during the failure mode of operation,
wherein the second power level is greater than the first power level.

18. An interleaved inverter comprising:
a plurality of module circuits including a plurality of switches;
a driving circuit configured to operate the plurality of module circuits in a normal mode of operation and a failure mode of operation,
wherein at least one of the plurality of module circuits operates at a first power level during the normal mode of operation and a second power level during the failure mode of operation,
wherein the second power level is greater than the first power level.

Assignees

• Kohler Co

Inventors

• Frampton Isaac S
• Larson Adam

Classifications

• H02M7/493 Primary

  the static converters being arranged for operation in parallel · CPC title

• H02M7/4803

  with means for reducing DC component from AC output voltage · CPC title

• H02M1/126

  using passive filters · CPC title

• H02M7/537

  using semiconductor devices only, e.g. single switched pulse inverters · CPC title

• H02M7/4807

  having a high frequency intermediate AC stage · CPC title