Phase-shifting optimization for asymmetric inductors in multi-phase DC-DC converters

Patent metadata

Field	Value
Publication number	US-10008918-B2
Application number	US-201615333230-A
Country	US
Kind code	B2
Filing date	Oct 25, 2016
Priority date	Oct 25, 2016
Publication date	Jun 26, 2018
Grant date	Jun 26, 2018

Abstract

A system is disclosed which provides the minimization of peak-to-peak output voltage ripple in multi-phase DC-DC switching converters, with two or more different value inductors (asymmetric inductors), by the optimization of phase-shifting determined by the inductance on each phase. An object of the disclosure is to ensure both the AC accuracy of the output voltage and the efficiency of the DC-DC switching converter is increased. The output voltage ripple improvement is shown to be dependent on the duty-cycle. Another object of the disclosure is to minimize the total inductor current ripple and improving the efficiency of the DC-DC switching converter by reducing the capacitor loss. Still another object of the disclosure is to minimize the output voltage ripple in the multi-phase DC-DC switching converter by ensuring the sum of the inductor current vectors is equal to zero.

First claim

The invention claimed is:

1. A multiphase DC-DC switching converter, comprising:
n phases, with a pair of power switches on each phase, where n is two or more;
n asymmetric inductors, each of said asymmetric inductors connected to one of said pairs of power switches;
a single output, connected in parallel to each of said asymmetric inductors;
an error amplifier having as inputs said single output and a reference voltage;
n comparators configured to compare an output of said error amplifier and n ramp generator output signals, resulting in n pulse width modulation (PWM) signals, configured to be used as input signals to said pairs of power switches; and
a clock generator, configured to generate n phase-shifted clock signals for said ramp generator output signals,
wherein a phase-shift configuration is determined by said asymmetric inductors of said phases and said phase-shifted clock signals.

2. The multiphase DC-DC switching converter of claim 1 , wherein said switching converter is a Buck, Boost, or Buck-Boost DC-DC switching converter.

3. The multiphase DC-DC switching converter of claim 1 , wherein said one or more of said n asymmetric inductors comprise an inductor value that differs from others of said asymmetric inductors.

4. The multiphase DC-DC switching converter of claim 1 , wherein a peak-to-peak output voltage ripple is determined by said phase-shift configuration.

5. The multiphase DC-DC switching converter of claim 4 , wherein said peak-to-peak output voltage ripple is determined by a sum of inductor current vectors.

6. The multiphase DC-DC switching converter of claim 5 , wherein said output voltage ripple is minimized by said sum of inductor current vectors being equal to zero.

7. The multiphase DC-DC switching converter of claim 1 , wherein said clock is a synchronous logic circuit.

8. The multiphase DC-DC switching converter of claim 7 , wherein said synchronous logic circuit comprises a clock generator set at a frequency higher than a DC-DC switching converter switching frequency.

9. The multiphase DC-DC switching converter of claim 1 , wherein said clock generator comprises a clock divider and delay lines.

10. The multiphase DC-DC switching converter of claim 9 , wherein a length of said delay line is based on a determined amount of phase-shifting.

11. The multiphase DC-DC switching converter of claim 1 , wherein said clock generator comprises a ring oscillator with variable delays.

12. The multiphase DC-DC switching converter of claim 11 , wherein said variable delays are based on a determined amount of phase-shifting.

13. The multiphase DC-DC switching converter of claim 1 , wherein said clock generator comprises a delay-locked loop (DLL).

14. The multiphase DC-DC switching converter of claim 13 , wherein a delay is based on a determined amount of phase-shifting.

15. A method for phase shift optimization using asymmetric inductors, comprising:
providing a multiphase DC-DC switching converter, with two or more phases, each of said phases having a pair of power switches;
providing two or more asymmetric inductors, each of said asymmetric inductors connected to one of said pairs of power switches;
providing a single output, connected in parallel to each of said asymmetric inductors; and
determining a phase shift configuration with said asymmetric inductors of said phases and phase-shifted clock signals.

16. The method of claim 15 , wherein said phase shift configuration determines a peak-to-peak output voltage ripple.

Assignees

• Dialog Semiconductor Uk Ltd

Inventors

• Wibowo Santhos Ario
• Kobayashi Hidenori
• Ozawa Seiichi
• Yokoyama Hidechika

Classifications

• H02M1/084 Primary

  using a control circuit common to several phases of a multi-phase system · CPC title

• H02M1/15

  using active elements · CPC title

• H02M3/1584 Primary

  with a plurality of power processing stages connected in parallel · CPC title

• H02M1/14

  Arrangements for reducing ripples from DC input or output · CPC title

• H02M3/158

  including plural semiconductor devices as final control devices for a single load · CPC title