Single capacitor multi-phase three-level buck voltage regulator

Patent metadata

Field	Value
Publication number	US-9600062-B2
Application number	US-201514682840-A
Country	US
Kind code	B2
Filing date	Apr 9, 2015
Priority date	Apr 9, 2015
Publication date	Mar 21, 2017
Grant date	Mar 21, 2017

Abstract

Methods and apparatus relating to a single capacitor multi-phase three-level buck Voltage Regulator (VR) are described. In an embodiment, voltage regulator logic includes a first phase portion and a second phase portion. The voltage regulator logic also includes a single capacitor coupled between switches of the first phase portion and the second phase portion. Other embodiments are also disclosed and claimed.

First claim

The invention claimed is:

1. An apparatus comprising:
voltage regulator logic having a first phase portion and a second phase portion; and
the voltage regulator logic to include a single capacitor coupled between switches of the first phase portion and the second phase portion, wherein the voltage regulator logic is a selectable-mode Voltage Regulator (VR) to implement one or more of a plurality of VR modes, wherein the plurality of voltage regulator logic modes is to comprise at least one of: a three-level buck voltage regulator, a traditional buck voltage regulator, and a combination of the three-level buck VR and the traditional buck VR.

2. The apparatus of claim 1 , wherein each of the first phase portion and the second phase portion is to comprise a plurality of switches.

3. The apparatus of claim 1 , wherein the switches of the first phase portion is to comprise a first switch, and a second switch, wherein a first end of the single capacitor is to be coupled between the first switch and the second switch of the first phase portion.

4. The apparatus of claim 3 , wherein the switches of the second phase portion is to comprise a third switch and a fourth switch, wherein a second end of the single capacitor is to be coupled between the third switch and the fourth switch of the second phase portion.

5. The apparatus of claim 1 , wherein the voltage regulator logic is to comprise a phase shifted filter network to reduce an output ripple.

6. The apparatus of claim 5 , wherein the phase shifted filter network is to comprise: an output capacitor, a first inductor, and a second inductor, wherein the first inductor is to be coupled to a first end of the single capacitor through a first switch of the first phase portion, wherein the second inductor is to be coupled to a second end of the single capacitor through a second switch of the second phase portion.

7. The apparatus of claim 1 , wherein at least one of the switches is to receive a control input from a controller logic.

8. The apparatus of claim 7 , wherein the controller logic comprises mode selection logic to select a VR mode.

9. The apparatus of claim 1 , wherein at least one of the switches is selected from the group comprising: field effect transistors (FETs), bipolar junction transistors (BJTs), insulated gate bipolar transistors (IGBTs), and relays.

10. The apparatus of claim 1 , wherein one or more of: the logic, a processor, and memory are on a single integrated circuit.

11. A computing system comprising:
memory to store data;
a processor, coupled to the memory, to perform one or more operations on the stored data; and
a selectable-mode voltage regulator (VR) to implement one or more of a plurality of VR modes, the selectable-mode VR comprising: a plurality of switches, a first inductor and a second inductor, a single fly capacitor, an output capacitor; and controller logic to manage operations of the selectable-mode VR,
wherein the single fly capacitor is to be coupled between a first phase portion and a second phase portion of the selectable-mode voltage regulator, wherein the plurality of voltage regulator logic modes is to comprise at least one of: a three-level buck voltage regulator, a traditional buck voltage regulator, and a combination of the three-level buck VR and the traditional buck VR.

12. The system of claim 11 , wherein each of the first phase portion and the second phase portion is to comprise two or more switches from the plurality of switches.

13. The system of claim 12 , wherein the two or more switches of the first phase portion is to comprise a first switch, and a second switch, wherein a first end of the single fly capacitor is to be coupled between the first switch and the second switch of the first phase portion.

14. The system of claim 13 , wherein the two or more switches of the second phase portion is to comprise a third switch and a fourth switch, wherein a second end of the single fly capacitor is to be coupled between the third switch and the fourth switch of the second phase portion.

15. The system of claim 11 , wherein the voltage regulator is to comprise a phase shifted filter network to reduce an output ripple.

16. The system of claim 15 , wherein the phase shifted filter network is to comprise: the output capacitor, the first inductor, and the second inductor, wherein the first inductor is to be coupled to a first end of the single fly capacitor through a first switch of the first phase portion, wherein the second inductor is to be coupled to a second end of the single fly capacitor through a second switch of the second phase portion.

17. The system of claim 11 , wherein at least one of the plurality of switches is to receive a control input from a controller logic.

18. The system of claim 17 , wherein the controller logic comprises mode selection logic to select a VR mode.

19. The system of claim 11 , wherein at least one of the plurality of switches is selected from the group comprising: field effect transistors (FETs), bipolar junction transistors (BJTs), insulated gate bipolar transistors (IGBTs), and relays.

20. The system of claim 11 , wherein the VR, the processor, and the memory are on a single integrated circuit.

Assignees

• Intel Corp

Inventors

• Kumar Pavan M

Classifications

• G06F1/26 Primary

  Power supply means, e.g. regulation thereof (for memories G11C) · CPC title

• H02M3/07

  using capacitors charged and discharged alternately by semiconductor devices with control electrode {, e.g. charge pumps} · CPC title

• G06F1/3296

  by lowering the supply or operating voltage · CPC title

• H02J7/345

  using capacitors as storage or buffering devices · CPC title

• H02M2003/1586

  Electricity · mapped topic