Multi-phase interleaved converter with automatic current-sharing function and control method therefor

Patent metadata

Field	Value
Publication number	US-9559591-B2
Application number	US-201514939037-A
Country	US
Kind code	B2
Filing date	Nov 12, 2015
Priority date	Dec 9, 2014
Publication date	Jan 31, 2017
Grant date	Jan 31, 2017

Abstract

A multi-phase interleaved converter can include: (i) a plurality of phases, where each phase of the multi-phase interleaved converter includes a buck-type power stage having a power switch, a freewheeling switch and an inductor, a switching control circuit and a reference signal generator, and where each switching control circuit includes: (ii) an adder that receives a ramp signal and a feedback signal that represents an output voltage, and generates a feedback voltage signal; (iii) a comparator that receives the feedback voltage signal and a reference voltage signal, and generates a comparator output signal; and (iv) a logic circuit that receives the comparator output signal and an output from an on time control circuit, and controls a switching operation of the power switch.

First claim

What is claimed is:

1. A multi-phase interleaved converter, comprising:
a) a plurality of phases, wherein each phase of said multi-phase interleaved converter comprises a buck-type power stage having a power switch, a freewheeling switch and an inductor, a switching control circuit and a reference signal generator, and wherein each switching control circuit comprises an adder, a comparator, an on time control circuit, and a logic circuit;
b) said adder being configured to receive a ramp signal and a feedback signal that represents an output voltage of said multi-phase interleaved converter, and to generate a feedback voltage signal;
c) said comparator being configured to receive said feedback voltage signal and a reference voltage signal, and to generate a comparator output signal;
d) said logic circuit being configured to receive said comparator output signal and an output from said on time control circuit, and to control a switching operation of said power switch; and
e) said reference signal generator being configured to provide said reference voltage signal of each phase according to an inductor current sense signal of each phase, such that current-sharing occurs between each of said plurality of phases.

2. The multi-phase interleaved converter of claim 1 , wherein said reference signal generator comprises:
a) a main channel reference signal generator configured to generate a first reference voltage signal; and
b) a plurality slave channel reference signal generators configured to generate remaining reference voltage signals using said first reference voltage signal.

3. The multi-phase interleaved converter of claim 2 , wherein:
a) said main channel reference signal generator comprises a main channel transconductance amplifier configured to receive said feedback signal and a reference signal, and to generate a main channel transconductance signal as said first reference voltage signal via a compensation circuit; and
b) each slave channel reference signal generator comprises a slave channel transconductance amplifier and a slave channel adder, said slave channel transconductance amplifier being configured to receive an inductor current sense signal of a first phase, and an inductor current of a phase other than said first phase, and to generate a corresponding slave channel transconductance signal, wherein said slave channel adder is configured to add said slave channel transconductance signal with said first reference voltage signal after being compensated via a compensation circuit to generate a corresponding reference voltage signal.

4. The multi-phase interleaved converter of claim 1 , wherein:
a) said logic circuit is configured to receive said comparator output signal, and to activate a switching control signal to turn on said power switch; and
b) said on time control circuit is configured to begin timing when said power switch is turned on, and to activate an off signal after a predetermined time has elapsed, wherein said logic circuit deactivates said switching control signal in response to said off signal being activated in order to turn off said power switch.

5. The multi-phase interleaved converter of claim 4 , wherein said on time control circuit comprises a phase-locked loop configured to receive a clock signal, and to generate said off signal.

6. The multi-phase interleaved converter of claim 5 , wherein a phase difference between two clock signals is predetermined.

7. A method of controlling a multi-phase interleaved converter, the method comprising:
a) providing a plurality of phases, wherein each phase of said multi-phase interleaved converter comprises a buck-type power stage having a power switch, a freewheeling switch and an inductor, a switching control circuit and a reference signal generator, and wherein each switching control circuit comprises an adder, a comparator, an on time control circuit, and a logic circuit;
b) receiving, by said adder, a ramp signal and a feedback signal that represents an output voltage of said multi-phase interleaved converter, and generating a feedback voltage signal;
c) receiving, by said comparator, said feedback voltage signal and a reference voltage signal, and generating a comparator output signal;
d) receiving, by said logic circuit, said comparator output signal and an output from said on time control circuit, and controlling a switching operation of said power switch; and
e) providing, by said reference signal generator, said reference voltage signal of each phase according to an inductor current sense signal of each phase, such that current-sharing occurs between each of said plurality of phases.

8. The method of claim 7 , wherein said providing said reference voltage signal of each phase comprises:
a) generating, by a main channel reference signal generator, a first reference voltage signal; and
b) generating, by a plurality slave channel reference signal generators, remaining reference voltage signals using said first reference voltage signal.

9. The method of claim 8 , further comprising:
a) receiving, by a main channel transconductance amplifier in said main channel reference signal generator, said feedback signal and a reference signal, and generating a main channel transconductance signal as said first reference voltage signal via a compensation circuit;
b) receiving, by a slave channel transconductance amplifier in each slave channel reference signal generator, an inductor current sense signal of a first phase, and an inductor current of a phase other than said first phase, and generating a corresponding slave channel transconductance signal; and
c) adding, by a slave channel adder in each slave channel reference signal generator, said slave channel transconductance signal with said first reference voltage signal, after being compensated via a compensation circuit, for generating a corresponding reference voltage signal.

10. The method of claim 7 , further comprising:
a) receiving, by said logic circuit, said comparator output signal, and activating a switching control signal to turn on said power switch;
b) beginning timing, by said on time control circuit, when said power switch is turned on, and activating an off signal after a predetermined time has elapsed; and
c) deactivating, by said logic circuit, said switching control signal in response to said off signal being activated in order to turn off said power switch.

11. The method of claim 10 , wherein said on time control circuit comprises a phase-locked loop for receiving a clock signal, and generating said off signal.

12. The method of claim 11 , further comprising predetermining a phase difference between two clock signals.

Assignees

• Silergy Semiconductor Technology Hangzhou Ltd

Inventors

• Hang Kailang
• Sun Liangwei

Classifications

• H02M3/1584 Primary

  with a plurality of power processing stages connected in parallel · CPC title

• H02M2003/1586

  Electricity · mapped topic

• H02M2001/0025

  Electricity · mapped topic

• H02M3/1586

  switched with a phase shift, i.e. interleaved · CPC title

• H02M1/0025

  Arrangements for modifying reference values, feedback values or error values in the control loop of a converter · CPC title