Multiple independent on-chip interconnect

Patent metadata

Field	Value
Publication number	US-11675722-B2
Application number	US-202117337805-A
Country	US
Kind code	B2
Filing date	Jun 3, 2021
Priority date	Apr 16, 2021
Publication date	Jun 13, 2023
Grant date	Jun 13, 2023

Abstract

In an embodiment, a system on a chip (SOC) comprises a semiconductor die on which circuitry is formed, wherein the circuitry comprises a plurality of agents and a plurality of network switches coupled to the plurality of agents. The plurality of network switches are interconnected to form a plurality of physical and logically independent networks. A first network of the plurality of physically and logically independent networks is constructed according to a first topology and a second network of the plurality of physically and logically independent networks is constructed according to a second topology that is different from the first topology. For example, the first topology may a ring topology and the second topology may be a mesh topology. In an embodiment, coherency may be enforced on the first network and the second network may be a relaxed order network.

First claim

What is claimed is:

1. A system comprising:
a plurality of processor clusters, where a given processor cluster comprises one or more processors;
a plurality of graphics processing units;
a plurality of memory controllers configured to control access to memory devices;
a plurality of agents; and
a plurality of network switches coupled to the plurality of processor clusters, the plurality of graphics processing units, the plurality of memory controllers, and the plurality of agents, wherein:
a first subset of the plurality of network switches are interconnected to form a central processing unit (CPU) network between the plurality of processor clusters and the plurality of memory controllers,
a second subset of the plurality of network switches are interconnected to form an input/output (I/O) network between the plurality of processor clusters, the plurality of agents, and the plurality of memory controllers,
a third subset of the plurality of network switches are interconnected to form a relaxed order network between the plurality of graphics processing units, selected ones of the plurality of agents, and the plurality of memory controllers,
the CPU network, the I/O network, and the relaxed order network are independent of each other,
the CPU network and the I/O network are coherent, and
the relaxed order network is non-coherent and has reduced ordering constraints compared to the CPU network and I/O network.

2. The system as recited in claim 1 wherein at least one of the CPU network, the I/O network, and the relaxed order network has a number of physical channels that differs from a number of physical channels on another one of the CPU network, the I/O network, and the relaxed order network.

3. The system as recited in claim 1 wherein the CPU network is a ring network.

4. The system as recited in claim 1 wherein the I/O network is a ring network.

5. The system as recited in claim 1 wherein the relaxed order network is a mesh network.

6. The system as recited in claim 1 wherein a first agent of the plurality of agents comprises an I/O cluster comprising a plurality of peripheral devices.

7. The system as recited in claim 6 wherein the I/O cluster further comprises a bridge coupled to the plurality of peripheral devices and further coupled to a first network switch in the second subset.

8. The system as recited in claim 1 further comprising a network interface circuit configured to convert communications from a given agent to communications for a given network of CPU network, the I/O network, and the relaxed order network, wherein the network interface circuit is coupled to one of the plurality of network switches in the given network.

9. A system on a chip (SOC) comprising a semiconductor die on which circuitry is formed, wherein the circuitry comprises:
a plurality of processor clusters, where a given processor cluster comprises one or more processors;
a plurality of graphics processing units;
a plurality of memory controllers configured to control access to memory devices;
a plurality of input/output (I/O) clusters, wherein a given I/O cluster comprises one or more peripheral devices; and
a plurality of network switches coupled to the plurality of processor clusters, the plurality of graphics processing units, the plurality of memory controllers, and the plurality of I/O clusters, wherein:
a first subset of the plurality of network switches are interconnected to form a central processing unit (CPU) network between the plurality of processor clusters and the plurality of memory controllers,
a second subset of the plurality of network switches are interconnected to form an I/O network between the plurality of processor clusters, the plurality of I/O clusters, and the plurality of memory controllers,
a third subset of the plurality of network switches are interconnected to form a relaxed order network between the plurality of graphics processing units, selected ones of the plurality of I/O clusters, and the plurality of memory controllers,
the CPU network, the I/O network, and the relaxed order network are independent of each other,
the CPU network and the I/O network are coherent, and
the relaxed order network is non-coherent and has reduced ordering constraints compared to the CPU network and I/O network.

10. The SOC as recited in claim 9 wherein at least one of the CPU network, the I/O network, and the relaxed order network has a number of physical channels that differs from a number of physical channels on another one of the CPU network, the I/O network, and the relaxed order network.

11. The SOC as recited in claim 9 wherein the CPU network is a ring network.

12. The SOC as recited in claim 9 wherein the I/O network is a ring network.

13. The SOC as recited in claim 9 wherein the relaxed order network is a mesh network.

14. The SOC as recited in claim 9 wherein the given I/O cluster further comprises a bridge coupled to the one or more peripheral devices and further coupled to a first network switch in the second subset.

15. The SOC as recited in claim 9 further comprising a network interface circuit configured to convert communications from a given agent to communications for a given network of CPU network, the I/O network, and the relaxed order network, wherein the network interface circuit is coupled to one of the plurality of network switches in the given network.

16. The SOC as recited in claim 9 wherein:
the CPU network includes one or more first virtual channels and the I/O network includes one or more second virtual channels; and
at least one of the one or more second virtual channels differs from the one or more first virtual channels.

17. The SOC as recited in claim 9 wherein a first processor cluster of the plurality of processor clusters is configured to generate a transaction to be transmitted, and wherein the first processor cluster is configured to select one of CPU network or the I/O network on which to transmit the transaction based on a type of the transaction.

18. The SOC as recited in claim 9 wherein:
the relaxed order network includes a plurality of virtual channels; and
transactions in different virtual channels of the plurality of virtual channels take different paths through the relaxed order network from a given source to a given target.

19. The SOC as recited in claim 9 wherein:
the relaxed order network is configured to route transactions from a given source to a given target, and wherein different paths through the relaxed order network from the given source to the given target are selected for the transactions based on one or more attributes of the transactions.

20. A method comprising:
generating a transaction in one of a plurality of processor clusters in a system, where a given processor cluster comprises one or more processors, and wherein the system further comprises:
a plurality of graphics processing units;
a plurality of memory controllers configured to control access to memory devices;
a plurality of agents; and
a plurality of network switches coupled to the plurality of processor clusters, the plurality of graphics processing units, the plurality of memory controllers, and the plurality of agents, wherein:
a first subset of the plurality of network switches are interconnected to form a central processing unit (CPU) network between the plurality of processor clusters and the plurality of memory controllers,
a second subset of the plurality of network switches are interconnected to form an input/output (I/O) network bet

Assignees

• Apple Inc

Inventors

• Kolor Sergio
• Tota Sergio V
• Zemer Tzach
• Lahav Sagi
• Redshaw Jonathan M
• Hammarlund Per H
• Tamari Eran
• Vash James
• Garg Gaurav
• Zimet Lior
• Kaushikkar Harshavardhan
• Fishwick Steven
• Hutsell Steven R
• Fukami Shawn M

Classifications

• G06F13/1668

  Details of memory controller · CPC title

• G06F13/4027 Primary

  using bus bridges (G06F13/4022 takes precedence) · CPC title

• G06F13/4022 Primary

  using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence) · CPC title

• G06F15/17381

  Two dimensional, e.g. mesh, torus · CPC title

• G06F15/17375

  One dimensional, e.g. linear array, ring · CPC title