Integrated circuit devices

Patent metadata

Field	Value
Publication number	US-11670676-B2
Application number	US-202117379051-A
Country	US
Kind code	B2
Filing date	Jul 19, 2021
Priority date	Dec 24, 2020
Publication date	Jun 6, 2023
Grant date	Jun 6, 2023

Abstract

An integrated circuit device includes: a fin-type active region on a substrate and including a fin top surface at a first level; a gate line on the fin-type active region; and an insulating structure on a sidewall of the fin-type active region. The insulating structure includes: a first insulating liner in contact with a sidewall of the fin-type active region; a second insulating liner on the first insulating liner and including an uppermost portion at a second level c than the first level; a lower buried insulating layer facing the sidewall of the fin-type active region and including a first top surface facing the gate line at a third level lower than the second level; and an upper buried insulating layer between the lower buried insulating layer and the gate line and including a second top surface at a fourth level equal to or higher than the second level.

First claim

What is claimed is:

1. An integrated circuit device comprising:
a fin-type active region extending in a first horizontal direction on a substrate and comprising a fin top surface at a first level;
a gate line extending in a second horizontal direction crossing the first horizontal direction on the fin-type active region; and
an insulating structure between the substrate and the gate line and on a sidewall of the fin-type active region,
wherein the insulating structure comprises:
a first insulating liner in contact with a sidewall of the fin-type active region;
a second insulating liner on the sidewall of the fin-type active region with the first insulating liner therebetween and comprising an uppermost portion at a second level that is closer to a bottom surface of the substrate than the first level;
a lower buried insulating layer on the sidewall of the fin-type active region with the first insulating liner and the second insulating liner therebetween and comprising a first top surface facing the gate line at a third level that is closer to the bottom surface of the substrate than the second level; and
an upper buried insulating layer between the lower buried insulating layer and the gate line and comprising a second top surface at a fourth level that is at a same distance or farther from the bottom surface of the substrate than the second level.

2. The integrated circuit device of claim 1 , wherein the upper buried insulating layer comprises a silicon oxide layer comprising at least one impurity element selected from nitrogen (N) and/or fluorine (F).

3. The integrated circuit device of claim 1 , wherein the upper buried insulating layer comprises:
a first silicon oxide layer comprising nitrogen (N) atom and/or fluorine (F); and
a second silicon oxide layer between the first silicon oxide layer and the gate line.

4. The integrated circuit device of claim 1 , wherein the insulating structure further comprises an upper insulating liner between the second insulating liner and the upper buried insulating layer and between the lower buried insulating layer and the upper buried insulating layer, and
wherein the upper insulating liner comprises a first part in contact with the uppermost portion of the second insulating liner and a second part in contact with the first top surface of the lower buried insulating layer.

5. The integrated circuit device of claim 1 , wherein the first insulating liner and the second insulating liner comprise different materials from each other.

6. The integrated circuit device of claim 1 , wherein the first top surface of the lower buried insulating layer has a concave shape toward the gate line, and
wherein a bottom surface of the upper buried insulating layer faces the first top surface and has a convex shape toward the substrate.

7. The integrated circuit device of claim 1 , wherein the second top surface of the upper buried insulating layer has a planar shape extending in the second horizontal direction.

8. The integrated circuit device of claim 1 , wherein the second top surface of the upper buried insulating layer has a convex shape toward the gate line.

9. The integrated circuit device of claim 1 , wherein the second top surface of the upper buried insulating layer has a concave shape toward the gate line.

10. The integrated circuit device of claim 1 , wherein the insulating structure further comprises an upper insulating liner that is between the second insulating liner and the upper buried insulating layer, and that is between the lower buried insulating layer and the upper buried insulating layer,
wherein the first insulating liner comprises a first silicon oxide layer,
wherein the second insulating liner comprises a silicon nitride layer,
wherein the lower buried insulating layer comprises a second silicon oxide layer,
wherein the upper insulating liner comprises a third silicon oxide layer,
wherein the upper buried insulating layer comprises a fourth silicon oxide layer comprising nitrogen (N) and/or fluorine (F), and
wherein a density of the second silicon oxide layer is lower than a respective density of each of the third silicon oxide layer and the fourth silicon oxide layer.

11. An integrated circuit device comprising:
a substrate comprising a device region and an inter-device isolation region defining the device region;
a fin-type active region extending in a first horizontal direction in the device region and comprising a fin top surface at a first level;
a nanosheet stack comprising at least one nanosheet on the fin top surface and spaced apart from the fin top surface in a vertical direction, each nanosheet of the nanosheet stack having a different vertical distance from the fin top surface;
a gate line on the at least one nanosheet on the fin-type active region, the gate line extending in a second horizontal direction crossing the first horizontal direction in the device region and the inter-device isolation region;
a first insulating structure between the substrate and the gate line in the device region and on a sidewall of the fin-type active region; and
a second insulating structure between the substrate and the gate line in the inter-device isolation region,
wherein the first insulating structure comprises:
a first insulating liner in contact with the sidewall of the fin-type active region;
a second insulating liner on the sidewall of the fin-type active region with the first insulating liner therebetween and comprising an uppermost portion at a second level that is closer to a bottom surface of the substrate than the first level;
a first lower buried insulating layer on the sidewall of the fin-type active region with the first insulating liner and the second insulating liner therebetween, and comprising a first top surface facing the gate line at a third level that is closer to the bottom surface of the substrate than the second level; and
a first upper buried insulating layer between the first lower buried insulating layer and the gate line and comprising a second top surface at a fourth level that is at a same distance or farther from the bottom surface of the substrate than the second level.

12. The integrated circuit device of claim 11 , wherein the second insulating structure comprises:
a second lower buried insulating layer between the substrate and the gate line and comprising a third top surface at a fifth level that is farther from the bottom surface of the substrate than the third level of the first lower buried insulating layer; and
a second upper buried insulating layer between the second lower buried insulating layer and the gate line and comprising a fourth top surface at a sixth level that is farther from the bottom surface of the substrate than the fourth level.

13. The integrated circuit device of claim 12 , wherein each of the first upper buried insulating layer and the second upper buried insulating layer comprises a silicon oxide layer comprising nitrogen (N) and/or fluorine (F).

14. The integrated circuit device of claim 12 , wherein each of the first upper buried insulating layer and the second upper buried insulating layer comprises:
a first silicon oxide layer comprising nitrogen (N) and/or fluorine (F); and
a second silicon oxide layer between the first silicon oxide layer and the gate line.

15. The integrated circuit device of claim 12 , wherein the first insulating structure further comprises a first upper insulating liner that is between the second insulating liner and the first upper buried insulating layer, and that is between the first lower buried insulating layer and the first upper buried insu

Assignees

• Samsung Electronics Co Ltd

Inventors

• Min Sunki
• Roh Donghyun
• Na Chaeho

Classifications

• B82Y10/00

  Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/6735

  having gates fully surrounding the channels, e.g. gate-all-around · CPC title

• H10D62/121 Primary

  oriented parallel to substrates · CPC title

• H10D84/0144

  Manufacturing their gate insulating layers · CPC title