Method of forming a FinFET having an oxide region in the source/drain region

Patent metadata

Field	Value
Publication number	US-9490348-B2
Application number	US-201313970295-A
Country	US
Kind code	B2
Filing date	Aug 19, 2013
Priority date	Jul 3, 2013
Publication date	Nov 8, 2016
Grant date	Nov 8, 2016

Abstract

Embodiments of the present disclosure include a semiconductor device, a FinFET device, and methods for forming the same. An embodiment is a semiconductor device including a first semiconductor fin extending above a substrate, the first semiconductor fin having a first lattice constant, an isolation region surrounding the first semiconductor fin, and a first source/drain region in the first semiconductor fin, the first source/drain having a second lattice constant different from the first lattice constant. The semiconductor device further includes a first oxide region along a bottom surface of the first source/drain region, the first oxide region extending into the isolation region.

First claim

What is claimed is:

1. A method for forming a fin field-effect transistor (FinFET) device, the method comprising:
forming a first semiconductor fin extending above a substrate, the first semiconductor fin having a first lattice constant;
forming an isolation region surrounding the first semiconductor fin;
forming a first source/drain region in the first semiconductor fin, the first source/drain region having a second lattice constant different from the first lattice constant; and
performing an oxidation process to the substrate to form a first oxide region in the first source/drain region, the first oxide region being along a bottom surface of the first source/drain region and extending into the isolation region, wherein the oxidation process comprises applying a reaction gas to the device so as to oxidize the bottom surface of the first source/drain region.

2. The method of claim 1 , wherein the step of performing the oxidation process to the substrate is after the forming the first source/drain region.

3. The method of claim 1 further comprising:
before performing the oxidation process to the substrate, forming an etch stop layer (ESL) on the first source/drain region; and
before performing the oxidation process to the substrate, forming an inter-layer dielectric on the ESL.

4. The method of claim 1 further comprising:
forming a second source/drain region in the first semiconductor fin, the second source/drain region having the second lattice constant; and
wherein the performing the oxidation process to the substrate further forms a second oxide region in the second source/drain region, the second oxide region being along a bottom surface of the second source/drain region and extending into the isolation region, a channel region in the first semiconductor fin being interposed between the first and second source/drain regions, the channel region having the first lattice constant.

5. The method of claim 4 , wherein the first and second oxide regions extend into the channel region.

6. The method of claim 4 further comprising:
forming a gate dielectric layer over the channel region; and
forming a gate electrode on the gate dielectric layer, the gate electrode being interposed between the first and second source/drain regions.

7. The method of claim 4 , wherein the first oxide region extends completely across the bottom surface of the first source/drain region.

8. The method of claim 4 , wherein the first oxide region has a different material composition than the isolation region.

9. A method comprising:
forming a semiconductor fin extending above a substrate, the semiconductor fin having a first lattice constant;
forming an isolation region surrounding the semiconductor fin;
removing a portion of the semiconductor fin to form a first recess, a channel region of the semiconductor fin being adjacent the first recess;
epitaxially growing a first material in the first recess to form a first source/drain region in the semiconductor fin, the first source/drain region having a second lattice constant different from the first lattice constant; and
performing an oxidation process to the substrate to form a first oxide region in the first source/drain region, the first oxide region adjoining a first interface between the first source/drain region and the channel region, the first oxide region extending into the isolation region, wherein the oxidation process comprises applying a reaction gas so as to form the first oxide region.

10. The method of claim 9 , wherein the first oxide region has a different material composition than the isolation region.

11. The method of claim 9 , wherein the first oxide region extends along a second interface between the first source/drain region and the semiconductor fin, the second interface being perpendicular to the first interface.

12. The method of claim 9 , wherein a top surface of the first oxide region is lower than a top surface of the isolation region.

13. The method of claim 9 , wherein the first oxide region comprises GeOx or SiGeOx.

14. The method of claim 9 further comprising:
before performing the oxidation process to the substrate, forming an etch stop layer (ESL) on the first source/drain region;
before performing the oxidation process to the substrate, forming an inter-layer dielectric on the ESL; and
wherein the step of performing the oxidation process to the substrate is after the forming the first source/drain region.

15. The method of claim 9 , wherein the first oxide region extends into the channel region.

16. A method comprising:
forming a first semiconductor fin extending above a substrate;
forming an isolation region surrounding the first semiconductor fin;
forming a dummy gate dielectric layer over the first semiconductor fin;
forming a dummy gate electrode on the dummy gate dielectric layer;
forming a first source/drain region and a second source/drain region in the first semiconductor fin, the dummy gate electrode being interposed between the first and second source/drain regions;
forming an etch stop layer (ESL) on the first and second source/drain regions;
forming an inter-layer dielectric (ILD) on the ESL;
removing the dummy gate electrode and dummy gate dielectric layer to expose a first portion of the first semiconductor fin; and
performing an oxidation process to the substrate to form a first oxide region in the first source/drain region and a second oxide region in the second source/drain region, the first oxide region being along a bottom surface of the first source/drain region and extending into the isolation region, the second oxide region being along a bottom surface of the second source/drain region and extending into the isolation region, wherein the ESL prevents oxidation of upper portions of the first and second source/drain regions during the oxidation process.

17. The method of claim 16 further comprising:
forming an active gate dielectric layer over the exposed first portion of the first semiconductor fin; and
forming an active gate electrode over the active gate dielectric layer.

18. The method of claim 16 , wherein the first and second oxide regions extend into the first portion of the first semiconductor fin.

19. The method of claim 16 further comprising:
forming a second semiconductor fin extending above the substrate, the second semiconductor fin being parallel to the first semiconductor fin, the isolation region surrounding the second semiconductor fin;
forming a third source/drain region and a fourth source/drain region in the second semiconductor fin; and
wherein the performing the oxidation process to the substrate forms a third oxide region along a bottom surface of the third source/drain region and a fourth oxide region along a bottom surface of the fourth source/drain region, the third oxide region and the fourth oxide region extending into the isolation region.

20. The method of claim 19 , wherein the first and second semiconductor fins extending from a raised portion of the substrate, the first and third source/drain regions being a first continuous source/drain region, the second and fourth source/drain regions being a second continuous source/drain region, the first and third oxide regions being a first continuous oxide region, and the second and fourth oxide regions being a second continuous oxide region.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Ching Kuo-Cheng
• Wang Chih-Hao
• Tsai Ching-Wei
• Wu Zhiqiang
• Colinge Jean-Pierre

Classifications

• H10P50/691

  for Group V materials or Group III-V materials · CPC title

• H10P50/242

  of Group IV materials · CPC title

• H10P14/6939

  characterised by the metal · CPC title

• H10P14/6903

  containing silicon · CPC title

• H10P14/6342

  Liquid deposition, e.g. spin-coating, sol-gel techniques or spray coating · CPC title