Integrated circuit device

Patent metadata

Field	Value
Publication number	US-10396205-B2
Application number	US-201815951385-A
Country	US
Kind code	B2
Filing date	Apr 12, 2018
Priority date	Sep 28, 2017
Publication date	Aug 27, 2019
Grant date	Aug 27, 2019

Abstract

An integrated circuit device includes a base burying insulating film covering a lower side wall of a fin-type active region on a substrate, an isolation pattern having a top surface higher than a top surface of the base burying insulating film, and a gate line covering a channel section of the fin-type active region. The gate line has an upper gate covering an upper portion of the channel section and a lower gate protruding from the upper gate toward the substrate and filling a space between a lower side wall of the channel section and an upper side wall of the isolation pattern.

First claim

What is claimed is:

1. An integrated circuit device, comprising:
a fin-type active region protruding from a substrate and extending longitudinally in a first horizontal direction;
a base burying insulating film including a vertical extension and a horizontal extension on the substrate, the vertical extension covering a lower side wall of the fin-type active region and having a first top surface at a first level, and the horizontal extension being integrally connected to the vertical extension and covering a top surface of the substrate;
an isolation pattern covering a side wall of the vertical extension on the horizontal extension and having a second top surface at a second level, the second level being higher than the first level; and
a gate line having an upper gate and a lower gate, the upper gate extending in a second horizontal direction crossing the first horizontal direction to cover an upper portion of a channel section of the fin-type active region and the second top surface of the isolation pattern, and the lower gate protruding from the upper gate toward the substrate and filling a space on the first top surface between a lower portion of the channel section and an upper side wall of the isolation pattern.

2. The integrated circuit device as claimed in claim 1 , wherein the vertical extension covers a side wall of a base section between the substrate and the channel section of the fin-type active region.

3. The integrated circuit device as claimed in claim 1 , wherein the base burying insulating film and the isolation pattern include different materials.

4. The integrated circuit device as claimed in claim 1 , wherein a dielectric constant of the base burying insulating film is lower than a dielectric constant of the isolation pattern.

5. The integrated circuit device as claimed in claim 1 , wherein the gate line includes a work function metal layer covering the channel section, and the lower gate is formed of part of the work function metal layer.

6. The integrated circuit device as claimed in claim 5 , wherein a first thickness of a first portion included in the lower gate in the work function metal layer is different from a second thickness of a second portion included in the upper gate in the work function metal layer.

7. The integrated circuit device as claimed in claim 1 , wherein the gate line includes a work function metal layer covering the channel section, and a first thickness of a first portion of the work function metal layer covering the lower portion of the channel section is different from a second thickness of a second portion of the work function metal layer covering the upper portion of the channel section.

8. The integrated circuit device as claimed in claim 7 , wherein the first thickness is greater than the second thickness.

9. The integrated circuit device as claimed in claim 7 , wherein the first thickness is less than the second thickness.

10. The integrated circuit device as claimed in claim 1 , wherein a thickness of a portion of the gate line covering the second top surface of the isolation pattern is less than a thickness of a portion of the gate line covering the vertical extension.

11. An integrated circuit device, comprising:
a substrate having an active region;
a plurality of fin-type active regions protruding from the active region and extending in a first horizontal direction in parallel with each other;
a base burying insulating film including a plurality of vertical extensions and a horizontal extension, the plurality of vertical extensions each filling a space between adjacent fin-type active regions among the plurality of fin-type active regions or covering a side wall of each of the plurality of fin-type active regions, and the horizontal extension being integrally connected to an outermost vertical extension among the plurality of vertical extensions and covering a top surface of the active region;
an isolation pattern separated from the fin-type active regions with the outermost vertical extension therebetween and having an upper side wall facing a channel section of an outermost fin-type active region among the plurality of fin-type active regions; and
a gate line extending in a second horizontal direction crossing the first horizontal direction to cover channel sections of the respective fin-type active regions, the base burying insulating film, and the isolation pattern,
wherein the gate line includes an upper gate covering an upper portion of the channel section of the outermost fin-type active region and a first lower gate filling a space between the upper side wall of the isolation pattern and a lower portion of the channel section of the outermost fin-type active region and protruding from the upper gate toward the substrate.

12. The integrated circuit device as claimed in claim 11 , wherein the gate line further includes a second lower gate protruding from the upper gate toward the substrate between two adjacent fin-type active regions among the plurality of fin-type active regions and covering a lower portion of a channel section of each of the two adjacent fin-type active regions.

13. The integrated circuit device as claimed in claim 12 , wherein a width of the second lower gate is greater than a width of the first lower gate in the second horizontal direction.

14. The integrated circuit device as claimed in claim 12 , wherein the plurality of vertical extensions include an inner vertical extension between the two adjacent fin-type active regions, and the second lower gate has a bottom surface facing the inner vertical extension.

15. The integrated circuit device as claimed in claim 11 , wherein the plurality of vertical extensions include an inner vertical extension between two adjacent fin-type active regions among the plurality of fin-type active regions, and a width of the outermost vertical extension is less than a width of the inner vertical extension in the second horizontal direction.

16. The integrated circuit device as claimed in claim 11 , wherein the gate line further includes a work function metal layer extending in the second horizontal direction to cover the channel sections of the respective fin-type active regions, and a thickness of a first portion forming the first lower gate in the work function metal layer is different from a thickness of a second portion forming the upper gate in the work function metal layer.

17. The integrated circuit device as claimed in claim 11 , wherein a thickness of a portion of the gate line covering a top surface of the isolation pattern is less than a thickness of a portion of the gate line covering the outermost vertical extension.

18. An integrated circuit device, comprising:
a device area defined by a device isolation area on a substrate;
a plurality of fin-type active regions each having a base section connected to the device area and a channel section on the base section;
a base burying insulating film including a plurality of vertical extensions and a horizontal extension, the vertical extensions being between the plurality of fin-type active regions and covering opposite side walls of the base section of each of the plurality of fin-type active regions, and the horizontal extension being integrally connected to an outermost vertical extension closest to the device isolation area among the plurality of vertical extensions and covering the device area;
a device isolation insulating film formed in the device isolation area and having a top surface higher than a top surface of the outermost vertical extension; and
an isolation pattern between

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Mun-Hyeon
• Whang Sung-Man
• Noh Chang-Woo
• Kim Dong-Won
• Oh Han-Su

Classifications

• H01L29/66795

  Electricity · mapped topic

• H01L29/0649

  Electricity · mapped topic

• H01L27/1203

  Electricity · mapped topic

• H01L21/8232

  Electricity · mapped topic

• H01L29/7851 Primary

  Electricity · mapped topic