STI shape near fin bottom of Si fin in bulk FinFET

Patent metadata

Field	Value
Publication number	US-9953885-B2
Application number	US-84369310-A
Country	US
Kind code	B2
Filing date	Jul 26, 2010
Priority date	Oct 27, 2009
Publication date	Apr 24, 2018
Grant date	Apr 24, 2018

Abstract

A method of forming an integrated circuit structure includes providing a semiconductor substrate including a top surface; forming a first insulation region and a second insulation region in the semiconductor substrate; and recessing the first insulation region and the second insulation region. Top surfaces of remaining portions of the first insulation region and the second insulation region are flat surfaces or divot surfaces. A portion of the semiconductor substrate between and adjoining removed portions of the first insulation region and the second insulation region forms a fin.

First claim

What is claimed is:

1. A method of forming an integrated circuit structure, the method comprising:
forming a plurality of shallow-trench isolation (STI) regions in a silicon substrate, wherein an entire portion of the silicon substrate disposed above bottommost surfaces of the plurality of STI regions comprises a semiconductor material;
removing top portions of the plurality of STI regions using HF and NH 3 as process gases to form a first silicon fin and a second silicon fin, wherein the first silicon fin and the second silicon fin are horizontally between, and above, remaining lower portions of the plurality of STI regions, and wherein one of the plurality of STI regions (an intermediate STI region) is between and contacting the first silicon fin and the second silicon fin and has a divot top surface, with the highest point of a top surface of the intermediate STI region being close to a middle line between the first silicon fin and the second silicon fin, and lower than top surfaces of the first and the second silicon fins, wherein the intermediate STI region comprises:
a liner contacting the first silicon fin and the second silicon fin; and
a dielectric region, wherein the liner contacts sidewalls and a bottom of the dielectric region, wherein the highest point of the top surface of the intermediate STI region is the highest point of both the liner and the dielectric region, and wherein the top surface of the intermediate STI region comprises:
a first region extending from the highest point of the top surface of the intermediate STI region toward a first sidewall of the first silicon fin, wherein magnitudes of slopes of the first region increase as the first region extends from the highest point of the top surface of the intermediate STI region toward the first sidewall of the first silicon fin;
a second region extending from the first sidewall of the first silicon fin toward the highest point of the top surface of the intermediate STI region, wherein the second region comprises a top surface of a vertical portion of the liner, and wherein the top surface of the vertical portion of the liner rises slightly as the top surface of the vertical portion of the liner extends toward the first sidewall of the first silicon fin; and
a third region interposed between the first region and the second region, wherein magnitudes of slopes of the third region decrease as the third region extends from the first region toward the second region, and wherein a first direction pointing from the highest point of the top surface of the intermediate STI region toward the first sidewall of the first silicon fin is perpendicular to a current flow direction through the first silicon fin; and
after removing the top portions of the plurality of STI regions, forming a FinFET comprising:
forming a gate dielectric on top surfaces and sidewalls of the first silicon fin and the second silicon fin, wherein the gate dielectric extends between the first sidewall of the first silicon fin and a second sidewall of the second silicon fin; and
forming a gate electrode on the gate dielectric, wherein the gate electrode extends from directly over the first silicon fin to directly over the second silicon fin.

2. The method of claim 1 , wherein the plurality of STI regions comprises silicon oxide.

3. The method of claim 1 , wherein a lowest point of the top surface of the intermediate STI region is close to, and is not, a joint point of the top surface of the intermediate STI region and the first sidewall of the first silicon fin.

4. The method of claim 1 , wherein the highest point and a lowest point of the top surface of the intermediate STI region have a height difference greater than about 5 nm.

5. The method of claim 1 , wherein the intermediate STI region is formed by steps comprising:
forming the liner contacting the first silicon fin and the second silicon fin; and
filling the dielectric region over a bottom portion of the liner, wherein the gate dielectric contacts the top surface of the vertical portion of the liner.

6. The method of claim 5 , wherein the forming the liner comprises a thermal oxidation, and the filling the dielectric region comprises a reaction using tetrathylorthosilicate (TEOS) and ozone as process gases.

7. The method of claim 1 , wherein the second region and the third region are portions of a concave region of the top surface of the intermediate STI region.

8. The method of claim 1 , wherein the first silicon fin and the second silicon fin have heights between about 15 nm and about 50 nm.

9. A method comprising:
etching a semiconductor substrate to form a trench extending into the semiconductor substrate, wherein remaining portions of the semiconductor substrate form a first semiconductor strip and a second semiconductor strip on opposite sides of the trench and wherein entireties of the first semiconductor strip and the second semiconductor strip comprise a semiconductor material;
forming a liner oxide extending to a bottom of the trench and on sidewalls of the first semiconductor strip and the second semiconductor strip;
filling a dielectric material into the trench and over the liner oxide;
planarizing the dielectric material, wherein the dielectric material and a remaining portion of the liner oxide in combination form a shallow-trench isolation (STI) region;
etching the STI region using HF and NH 3 as process gases, wherein a remaining portion of the STI region has a top surface having:
a convex region including a highest point of the top surface substantially at a middle line between the first semiconductor strip and the second semiconductor strip; and
a first concave region including a lowest point of the top surface close to a vertical interface between the dielectric material and a vertical portion of the liner oxide, wherein the first concave region is interposed between the vertical interface and the convex region along a first direction pointing from the highest point to the vertical interface, wherein a top surface of the vertical portion of the liner oxide rises slightly from the vertical interface toward the first semiconductor strip along the first direction, and wherein the first direction is perpendicular to a current flow direction through the first semiconductor strip; and

after etching the STI region, forming a FinFET comprising:
forming a gate dielectric on the sidewalls of the first semiconductor strip and the second semiconductor strip, the gate dielectric extending over the bottom of the trench and directly contacting the top surface of the STI region; and
forming a gate electrode over the gate dielectric, the gate electrode extending above top surfaces of the first semiconductor strip and the second semiconductor strip.

10. The method of claim 9 , wherein the forming the STI region comprises forming a silicon oxide region.

11. The method of claim 9 , wherein at the lowest point, the top surface is substantially flat.

12. The method of claim 9 , wherein the highest point and the lowest point have a height difference greater than about 5 nm.

13. The method of claim 9 , wherein the highest point of the top surface of the STI region is the highest point of both the liner oxide and the dielectric material.

14. The method of claim 9 , wherein the top surface of the STI region further has a second concave region, the convex region being interposed between the first concave region and the second concave region along the first direction.

15. The method of claim 9 , wherein the gate dielectric completely covers the top surface of the STI region.

16. A method comprising:

Assignees

• Yuan Feng
• Lee Tsung Lin
• Chen Hung Ming
• Chang Chang Yun
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Yuan Feng
• Lee Tsung-Lin
• Chen Hung-Ming
• Chang Chang-Yun

Classifications

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10D30/024

  of fin field-effect transistors [FinFET] · CPC title

• H01L21/823431

  Electricity · mapped topic

• H01L29/66795

  Electricity · mapped topic