Semiconductor package having a high reliability

Patent metadata

Field	Value
Publication number	US-11664352-B2
Application number	US-202117329036-A
Country	US
Kind code	B2
Filing date	May 24, 2021
Priority date	Feb 22, 2016
Publication date	May 30, 2023
Grant date	May 30, 2023

Abstract

A semiconductor package includes a package substrate, a plurality of semiconductor devices stacked on the package substrate, a plurality of underfill fillets disposed between the plurality of semiconductor devices and between the package substrate and the plurality of semiconductor devices, and a molding resin at least partially surrounding the plurality of semiconductor devices and the plurality of underfill fillets. The plurality of underfill fillets include a plurality of protrusions that protrude from spaces between each of the plurality of semiconductor devices or between the package substrate and each of the plurality of semiconductor devices. At least two neighboring underfill fillet protrusions of the plurality of protrusions form one continuous structure without an interface therebetween.

First claim

What is claimed is:

1. A semiconductor package, comprising:
a printed circuit board (PCB);
a first semiconductor device connected to the PCB by a first connection terminal;
a second semiconductor device connected to the first semiconductor device by a second connection terminal;
a first underfill fillet having a first height between the PCB and the first semiconductor device;
a second underfill fillet having a second height between the first semiconductor device and the second semiconductor device;
a top semiconductor device above the second semiconductor device;
a thermal interface material (TIM) layer on the top semiconductor device; and
a heat dissipation member on the TIM layer;
wherein the first underfill fillet has a first protrusion from a side surface of the first semiconductor device and the second underfill fillet has a second protrusion from a side surface of the second semiconductor device, the first protrusion has a first dimension in a horizontal direction parallel to an upper surface of the PCB, the second protrusion has a second dimension in the horizontal direction, and the first dimension is greater than the second dimension,
wherein the first underfill fillet has a third dimension from a side surface of the second semiconductor device to an outer end of the first protrusion in a horizontal direction parallel to an upper surface of the PCB, and the third dimension is greater than the second dimension, and
wherein the first height is greater than the second height.

2. A semiconductor package, comprising:
a package substrate;
a first semiconductor device connected to the package substrate by a first connection terminal;
a second semiconductor device connected to the first semiconductor device by a second connection terminal;
a first underfill fillet having a first height between the package substrate and the first semiconductor device; and
a second underfill fillet having a second height between the first semiconductor device and the second semiconductor device,
wherein the first height is greater than the second height.

3. The semiconductor package of claim 2 , wherein each of the first height and the second height ranges from about 5 μm to about 100 μm.

4. The semiconductor package of claim 2 , wherein the first underfill fillet has a first protrusion from a side surface of the first semiconductor device and the second underfill fillet has a second protrusion from a side surface of the second semiconductor device,
the first protrusion has a first dimension in a horizontal direction parallel to an upper surface of the package substrate, the second protrusion has a second dimension in the horizontal direction, and the first dimension is greater than the second dimension.

5. The semiconductor package of claim 4 , wherein the first underfill fillet has a third dimension from a side surface of the second semiconductor device to an outer end of the first protrusion in a horizontal direction parallel to an upper surface of the package substrate, and the third dimension is greater than the second dimension.

6. The semiconductor package of claim 2 , further comprising:
a third underfill fillet on the second semiconductor device;
a third semiconductor device on the third underfill fillet;
a fourth underfill fillet on the third semiconductor device; and
a fourth semiconductor device on the fourth underfill fillet,
wherein the second underfill fillet has a height greater than that of the third underfill fillet, and the third underfill fillet has a height greater than that of the fourth underfill fillet.

7. The semiconductor package of claim 6 , wherein an upper surface of the fourth semiconductor device is not covered by the fourth underfill fillet.

8. The semiconductor package of claim 6 , wherein an upper surface of the fourth semiconductor device is partially covered by the fourth underfill fillet.

9. The semiconductor package of claim 6 , further comprising a heat dissipation member on the fourth semiconductor device.

10. The semiconductor package of claim 9 , wherein the thermal interface material (TIM) layer is disposed between the heat dissipation member and the fourth semiconductor device.

11. The semiconductor package of claim 2 , wherein the package substrate is a printed circuit board (PCB).

12. The semiconductor package of claim 2 , further comprising a molding resin at least partially surrounding the first semiconductor device and the second semiconductor device.

13. A semiconductor package, comprising:
a package substrate;
a first semiconductor device connected to the package substrate by a first connection terminal;
a second semiconductor device connected to the first semiconductor device by a second connection terminal;
a first underfill fillet between the package substrate and the first semiconductor device; and
a second underfill fillet between the first semiconductor device and the second semiconductor device,
wherein the first underfill fillet has a first protrusion from a side surface of the first semiconductor device and the second underfill fillet has a second protrusion from a side surface of the second semiconductor device,
the first protrusion has a first dimension in a horizontal direction parallel to an upper surface of the package substrate, the second protrusion has a second dimension in the horizontal direction, and the first dimension is greater than the second dimension, and
the first underfill fillet has a first height ranging from about 5 μm to about 40 μm between the package substrate and the first semiconductor device, the second underfill fillet has a second height of about 5 μm or greater and less than about 40 μm between the first semiconductor device and the second semiconductor device, and the first height is greater than the second height.

14. The semiconductor package of claim 13 , wherein the package substrate is an interposer.

15. The semiconductor package of claim 13 , further comprising a top semiconductor device above the second semiconductor device and a top underfill fillet between the top semiconductor device and the second semiconductor device, wherein a top surface of the top semiconductor device is exposed from the top underfill fillet.

16. The semiconductor package of claim 13 , wherein the first underfill fillet has a third dimension from a side surface of the second semiconductor device to an outer end of the first protrusion in the horizontal direction parallel to an upper surface of the package substrate, and the third dimension is greater than the second dimension.

17. The semiconductor package of claim 13 , further comprising:
a third underfill fillet on the second semiconductor device;
a third semiconductor device on the third underfill fillet;
a fourth underfill fillet on the third semiconductor device; and
a fourth semiconductor device on the fourth underfill fillet,
wherein the second underfill fillet has a height greater than that of the third underfill fillet, and the third underfill fillet has a height greater than that of the fourth underfill fillet.

18. The semiconductor package of claim 17 , further comprising a molding resin surrounding side surfaces of the first to the fourth semiconductor devices, wherein an upper surface of the fourth semiconductor device is exposed from the molding resin.

19. The semiconductor package of claim 18 , wherein the upper surface of the fourth semiconductor device is coplanar with an upper surface of the molding resin.

20. The semiconductor package of claim 13

Assignees

• Samsung Electronics Co Ltd

Inventors

• Hwang Ji-Hwan
• Park Sang-Sick
• Min Tae-Hong
• NAM Geol

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/732

  between stacked chips · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title