Semiconductor package including underfill material layer and method of forming the same

Patent metadata

Field	Value
Publication number	US-11404395-B2
Application number	US-202017036508-A
Country	US
Kind code	B2
Filing date	Sep 29, 2020
Priority date	Nov 15, 2019
Publication date	Aug 2, 2022
Grant date	Aug 2, 2022

Abstract

A semiconductor package and a method of forming the same are provided. The semiconductor package includes one or a plurality of chips on a substrate, bumps disposed below each of the one or plurality of chips, an underfill material layer on the substrate, on a side surface of each of the bumps, and extending to side surfaces of the one or plurality of chips, and a mold layer on the substrate and contacting the underfill material layer. The underfill material layer includes a first side portion, a second side portion on the first side portion and having a slope, steeper than a slope of the first side portion, and a third side portion on the second side portion and having a slope that is less steep than a slope of the second side portion.

First claim

What is claimed is:

1. A semiconductor package comprising:
a plurality of stacked chips on a substrate and spaced apart from each other in a vertical direction, the plurality of stacked chips including a lower chip and an upper chip, wherein the vertical direction is a direction substantially perpendicular to an upper surface of the substrate;
lower bumps between the lower chip and the substrate;
interlayer bumps between adjacent chips among the plurality of stacked chips;
a mold layer on the substrate; and
an underfill material layer on the substrate,
wherein the underfill material layer comprises a lower portion, an interlayer portion, and a side portion,
wherein the lower portion of the underfill material layer is on a side surface of each of the lower bumps and is in a space between the lower chip and the substrate,
wherein the interlayer portion is on a side surface of each of the interlayer bumps and is in a space between adjacent chips among the plurality of stacked chips,
wherein the side portion extends from the lower portion and the interlayer portion and is adjacent to side surfaces of the plurality of stacked chips,
wherein the side portion of the underfill material layer comprises a first side portion, a second side portion on the first side portion, and a third side portion on the second side portion,
wherein a slope of the second side portion is steeper than a slope of the first side portion,
wherein the slope of the second side portion is steeper than a slope of the third side portion,
wherein the first side portion continuously extends from the upper surface of the substrate toward a lower end of the second side portion,
wherein the second side portion overlaps at least two chips adjacent to each other, among the plurality of stacked chips, in a horizontal direction,
wherein the horizontal direction is substantially parallel to the upper surface of the substrate, and
wherein at least a portion of the mold layer is on the side portion of the underfill material layer.

2. The semiconductor package according to claim 1 , wherein the side portion of the underfill material layer further comprises a lower curved portion between the first side portion and the second side portion.

3. The semiconductor package according to claim 1 , wherein the side portion of the underfill material layer further comprises an upper curved portion between the second side portion and the third side portion.

4. The semiconductor package according to claim 1 , further comprising:
a heat transfer material layer; and
a heat dissipation member on the heat transfer material layer,
wherein the heat dissipation member contacts the heat transfer material layer, and
wherein the heat transfer material layer is in contact with the upper chip and the mold layer.

5. The semiconductor package according to claim 4 , wherein an upper end of the side portion of the underfill material layer is in contact with the heat transfer material layer.

6. The semiconductor package according to claim 5 ,
wherein a thickness of the upper chip of the plurality of stacked chips is greater than a thickness of remaining ones of the plurality of stacked chips,
wherein the side portion of the underfill material layer is in contact with a portion of a side surface of the upper chip, and
wherein the mold layer is in contact with a remaining portion of the side surface of the upper chip.

7. The semiconductor package according to claim 1 ,
wherein the side portion of the underfill material layer further comprises a third side portion on the second side portion, and
wherein the third side portion is inclined with respect to the vertical direction,
wherein the third side portion is spaced apart from the upper surface of the substrate, and
wherein the third side portion is spaced apart from the upper chip.

8. The semiconductor package according to claim 1 ,
wherein the plurality of stacked chips further comprise one or a plurality of intermediate chips between the upper chip and the lower chip,
wherein each of the one or the plurality of intermediate chips, the upper chip and the lower chip comprises a lower chip base having a first surface and a second surface opposing each other, first chip pads on the first surface, second chip pads on the second surface, and through electrode structures electrically connecting the first chip pads and the second chip pads, and
wherein the upper chip comprises an upper chip base and upper chip pads on upper chip pads.

9. The semiconductor package according to claim 8 ,
wherein each of the upper chip base and the lower chip base comprises an internal circuit region, and
wherein the underfill material layer is on a side of the internal circuit region of the upper chip base and a side of the internal circuit region of the lower chip base.

10. The semiconductor package according to claim 1 ,
wherein the mold layer is spaced apart from the substrate, and
wherein the underfill material layer extends between the mold layer and the substrate.

11. The semiconductor package according to claim 1 , wherein at least one of the lower bumps and the interlayer bumps comprises a lower portion and an upper portion of an asymmetrical structure.

12. The semiconductor package according to claim 1 ,
wherein the underfill material layer comprises a first filler,
wherein the mold layer comprises a second filler, and
wherein a diameter of the second filler is greater than a diameter of the first filler.

13. The semiconductor package according to claim 1 , further comprising:
a printed circuit board;
a package substrate on the printed circuit board;
a semiconductor chip on the package substrate;
one or a plurality of stacked chip packages on the package substrate;
a heat dissipation member on the printed circuit board and overlapping the semiconductor chip and the one or plurality of stacked chip packages; and
a heat transfer material layer that is between the heat dissipation member and the semiconductor chip, and is between the heat dissipation member and the one or plurality of stacked chip packages,
wherein each of the one or plurality of stacked chip packages comprises the substrate, the plurality of stacked chips, the lower bumps, the interlayer bumps, the mold layer, and the underfill material layer,
wherein at least a portion of the plurality of stacked chips comprises a memory semiconductor chip, and
wherein the semiconductor chip is a central processing unit (CPU) semiconductor chip or a graphics processing unit (GPU) semiconductor chip.

14. The semiconductor package according to claim 13 , further comprising:
a first underfill material layer between the package substrate and the substrate and extending onto a side surface of the substrate in the one or plurality of stacked chip packages,
wherein the first underfill material layer is spaced apart from the underfill material layer of the one or plurality of stacked chip packages.

15. The semiconductor package according to claim 13 , further comprising:
a first underfill material layer between the package substrate and the substrate,
wherein the first underfill material layer extends onto a side surface of the substrate in the one or plurality of stacked chip packages, and
wherein the first underfill material layer contacts the underfill material layer of the one or plurality of stacked chip packages.

16. A semiconductor package comprising:
one or a plurality of chips on a substrate;
bumps below each of the one or plurality of chips; and
an underfill material layer on the substrate, on a side surfa

Assignees

• Samsung Electronics Co Ltd

Inventors

• Hwang Jihwan
• Kim Taehun
• Suh Jihwan
• Lee Soyoun
• Lee Hyuekjae
• Hong Jiseok

Classifications

• H10W90/722

  between stacked chips · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/291

  characterised by containers, encapsulations, or other housings for the stacked chips · CPC title

• H10W90/288

  characterised by arrangements for thermal management of the stacked chips · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title