Semiconductor device and method for manufacturing the same
US-2016365433-A1 · Dec 15, 2016 · US
Super junction semiconductor device having a compensation structure
US9570596B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9570596-B2 |
| Application number | US-201514679483-A |
| Country | US |
| Kind code | B2 |
| Filing date | Apr 6, 2015 |
| Priority date | May 1, 2013 |
| Publication date | Feb 14, 2017 |
| Grant date | Feb 14, 2017 |
How to read this patent
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
- Title
What the patent document calls the invention.
- Abstract
A short plain-language summary of the technical disclosure.
- Assignees and inventors
Who owns or filed the patent and who is credited as inventor.
- Key dates
Filing, priority, publication, and grant dates set the timeline.
- First independent claim
The legal scope of protection — read this for what is actually claimed.
- CPC / IPC classifications
Technology tags used to group this patent with similar filings.
- Citations and related patents
Prior art links and similar publications in this corpus.
Abstract
Official abstract text for this publication.
A super junction semiconductor device includes a semiconductor portion including mesa regions protruding from a base section and spatially separated in a lateral direction parallel to a first surface of the semiconductor portion, and a compensation structure covering at least sidewalls of the mesa regions. The compensation structure includes at least two first compensation layers of a first conductivity type, at least two second compensation layers of a complementary second conductivity type, and at least one interdiffusion layer between one of the first and one of the second compensation layers.
First claim
Opening claim text (preview).
What is claimed is: 1. A super junction semiconductor device, comprising: a semiconductor portion comprising mesa regions protruding from a base section and spatially separated in a lateral direction parallel to a first surface of the semiconductor portion; and a compensation structure covering at least sidewalls of the mesa regions, the compensation structure comprising at least two first compensation layers of a first conductivity type, at least two second compensation layer of a complementary second conductivity type, and at least one interdiffusion layer between one of the first and one of the second compensation layers, wherein the compensation structure covers portions of the end faces of the mesa regions, surficial lateral faces of the compensation structures cut the first and second compensation layers in a vertical projection of the mesa regions, and the super junction semiconductor device comprises body zones of the second conductivity type extending along the surficial lateral faces and structurally connecting the second compensation layers. 2. The super junction semiconductor device of claim 1 , wherein the compensation structure covers portions of the base section and buried lateral faces of the compensation structure cut the first and second compensation layers between the mesa regions, and the super junction semiconductor device comprises drain connection structures of the first conductivity type extending along the buried lateral faces and structurally connecting the first compensation layers.
Assignees
Inventors
Classifications
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Patent family
Related publications grouped by family.
External sources
Frequently asked questions
Answers are generated from the same data shown on this page.
- What does patent US9570596B2 cover?
- A super junction semiconductor device includes a semiconductor portion including mesa regions protruding from a base section and spatially separated in a lateral direction parallel to a first surface of the semiconductor portion, and a compensation structure covering at least sidewalls of the mesa regions. The compensation structure includes at least two first compensation layers of a first con…
- Who is the assignee on this patent?
- Infineon Technologies Austria Ag
- What technology area does this patent fall under?
- Primary CPC classification H01L29/7396. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Feb 14 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).