Semiconductor devices including thick pad

Patent metadata

Field	Value
Publication number	US-11652076-B2
Application number	US-202217736536-A
Country	US
Kind code	B2
Filing date	May 4, 2022
Priority date	Jan 15, 2020
Publication date	May 16, 2023
Grant date	May 16, 2023

Abstract

A semiconductor device may include a semiconductor chip in an encapsulant. A first insulation layer may be disposed on the encapsulant and the semiconductor chip. A horizontal wiring and a primary pad may be disposed on the first insulation layer. A secondary pad may be disposed on the primary pad. A second insulation layer covering the horizontal wiring may be disposed on the first insulation layer. A solder ball may be disposed on the primary pad and the secondary pad. The primary pad may have substantially the same thickness as a thickness of the horizontal wiring.

First claim

What is claimed is:

1. A method of manufacturing semiconductor device, the method comprising:
forming a first insulating layer on a semiconductor chip, an encapsulant in contact with the semiconductor chip, and through electrodes spaced apart from the semiconductor chip;
forming a first seed layer on the first insulating layer;
forming a horizontal wiring and a primary pad on the first seed layer;
forming a secondary pad on the primary pad;
partially removing the first seed layer to expose the first insulating layer;
forming a second insulating layer on the first insulating layer; and
forming solder balls on the primary pad and the secondary pad;
wherein an uppermost surface of the second insulation layer is farther from an upper surface of the first insulation layer than a top surface of the secondary pad, and
the upper surface of the primary pad is above a lowermost surface of the second insulating layer.

2. The method of claim 1 , wherein the forming the horizontal wiring and the primary pad comprises forming a conductive core,
wherein the first seed layer surrounds a side surface and a bottom of the conductive core.

3. The method of claim 1 , wherein the forming the horizontal wiring and the primary pad comprises forming a first mask pattern on the first seed layer,
wherein the first mask pattern exposes a portion of the first seed layer.

4. The method of claim 3 , wherein the forming the secondary pad on the primary pad comprises:
exposing the first seed layer by removing the first mask pattern; and
forming a second mask pattern covering the first seed layer and the horizontal wiring and covering a part of the primary pad.

5. The method of claim 4 , wherein the partially removing the first seed layer to expose the first insulating layer comprises exposing the first seed layer by removing the second mask pattern.

6. The method of claim 1 , the method further comprises forming a first barrier layer on the first insulating layer before forming the first seed layer.

7. The method of claim 1 , wherein the horizontal wiring and the primary pad have substantially the same thickness.

8. A method of manufacturing semiconductor device, the method comprising:
forming a first insulating layer on a semiconductor chip, an encapsulant in contact with the semiconductor chip, and through electrodes spaced apart from the semiconductor chip;
forming a first seed layer on the first insulating layer;
forming a primary pad on the first seed layer;
forming a second seed layer on the first seed layer and the primary pad;
forming a secondary pad on the second seed layer, the secondary pad being aligned on the primary pad;
partially removing the first seed layer and the second seed layer to expose the first insulating layer;
forming a second insulating layer on the first insulating layer; and
forming solder balls on the primary pad and the secondary pad;
wherein an uppermost surface of the second insulation layer is farther from an upper surface of the first insulation layer than a top surface of the secondary pad, and
the upper surface of the primary pad is above a lowermost surface of the second insulating layer.

9. The method of claim 8 , wherein the forming the primary pad comprises forming a first mask pattern on the first seed layer,
wherein the first mask pattern exposes a portion of the first seed layer.

10. The method of claim 8 , the method further comprises forming a horizontal wiring on the first seed layer,
wherein the horizontal wiring and the primary pad have substantially the same thickness.

11. The method of claim 8 , wherein the forming the primary pad comprises forming a conductive core,
wherein the first seed layer surrounds a side surface and a bottom of the conductive core.

12. The method of claim 8 , wherein the forming the secondary pad on the second seed layer comprises forming a second mask pattern on the second seed layer.

13. The method of claim 12 , wherein the partially removing the first seed layer and the second seed layer to expose the first insulating layer comprises exposing the second seed layer by removing the second mask pattern.

14. The method of claim 8 , the method further comprises forming a first barrier layer on the first insulating layer before forming the first seed layer.

15. The method of claim 8 , wherein the partially removing the first seed layer and the second seed layer to expose the first insulating layer comprises forming an undercut region between the secondary pad and the primary pad,
wherein the solder balls extend in the undercut region and contact a lower surface of the secondary pad and a side surface of the second seed layer.

16. The method of claim 8 , wherein the encapsulant is disposed between the through electrodes and the semiconductor chip.

17. A method of manufacturing semiconductor device, the method comprising:
forming a first insulating layer on a semiconductor chip, an encapsulant in contact with the semiconductor chip, and through electrodes spaced apart from the semiconductor chip;
forming a first seed layer on the first insulating layer;
forming a first mask pattern on the first seed layer;
forming a horizontal wiring and a primary pad in the first mask pattern, on the first seed layer;
removing the first mask pattern;
forming a second mask pattern on the first seed layer, the horizontal wiring, and the primary pad;
forming a secondary pad in the second mask pattern, on the primary pad;
removing the second mask pattern;
removing a portion of the first seed layer;
forming a second insulating layer on the first insulating layer; and
forming a solder ball on the secondary pad;
wherein an uppermost surface of the second insulation layer is farther from an upper surface of the first insulation layer than a top surface of the secondary pad, and
the upper surface of the primary pad is above a lowermost surface of the second insulating layer.

18. The method of claim 17 , wherein the horizontal wiring and the primary pad have substantially the same thickness.

19. The method of claim 17 , wherein the second insulating layer covers an edge of the primary pad, and
wherein the solder ball extends in the second insulating layer, contacts a top surface of the primary pad, and contacts a top surface and side surfaces of the secondary pad.

20. The method of claim 17 , wherein the first seed layer is connected to the through electrodes and a chip pad of the semiconductor chip.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Ko Taeho
• Lee Daehee
• Jung Hyunchul

Classifications

• H10W90/00 Primary

  Package configurations · CPC title

• H10W72/01935

  by plating, e.g. electroless plating or electroplating · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/942

  relative to underlying supporting features, e.g. bond pads, RDLs or vias · CPC title

• H10W72/934

  Cross-sectional shape, i.e. in side view · CPC title