Wafer-level stack chip package and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-2016133601-A1
Application number	US-201514931112-A
Country	US
Kind code	A1
Filing date	Nov 3, 2015
Priority date	Nov 5, 2014
Publication date	May 12, 2016
Grant date	—

Abstract

A semiconductor product in the form of a stack chip package and a method of manufacturing the same, where a plurality of semiconductor chips are stacked one on another so as to enable the exchange of electrical signals between the semiconductor chips, and where a conductive layer is included for inputting and outputting signals to and from individual chips. A stack chip package having a compact size may, for example, be manufactured by stacking, on a first semiconductor chip, a second semiconductor chip having a smaller surface area by means of interconnection structures so as to enable the exchange of electrical signals between the first and second semiconductor chips, and by using a conductive layer for inputting and outputting signals to and from individual semiconductor chips, in lieu of a thick substrate. Furthermore, heat dissipation effects can be enhanced by the addition of a heat dissipation unit.

First claim

What is claimed is:

1 . A semiconductor product, comprising:
a first semiconductor chip comprising a first surface and a second surface opposite the first surface of the first semiconductor chip; a first interconnection structure coupled to a first bonding pad on the first surface of the first semiconductor chip; a second semiconductor chip comprising a first surface and a second surface opposite the first surface of the second semiconductor chip, the first surface of the second semiconductor chip comprising a bonding pad; a second interconnection structure coupled to the bonding pad on the first surface of the second semiconductor chip, wherein the bonding pad on the first surface of the second semiconductor chip is coupled to a second bonding pad on the first surface of the first semiconductor chip; an encapsulating material encapsulating at least the first surface of the first semiconductor chip and the first interconnection structure; a conductive layer coupled to the first interconnection structure at a surface of the encapsulating material; and a third interconnection structure coupled to the conductive layer.

2 . The semiconductor product of claim 1 , wherein the surface area of the first surface of the first semiconductor chip is larger than the surface area of the first surface of the second semiconductor chip.

3 . The semiconductor product of claim 1 , wherein the second bonding pad is located in a central region of the first surface of the first semiconductor chip, and the first bonding pad is located in a peripheral region of the first surface of the first semiconductor chip outside of the central region.

4 . The semiconductor product of claim 1 , wherein the second surface of the first semiconductor chip and one or more side surfaces connecting the first surface and the second surface of the first semiconductor chip are exposed.

5 . The semiconductor product of claim 1 , wherein the first interconnection structure comprises a conductive pillar.

6 . The semiconductor product of claim 1 , wherein the third interconnection structure comprises a solder ball.

7 . The semiconductor product of claim 1 , wherein side surfaces of the first semiconductor chip, the encapsulating material, and a redistribution layer are coplanar.

8 . The semiconductor product of claim 1 , wherein the first semiconductor chip comprises a memory device of a first storage capacity, and the second semiconductor chip comprises a memory device of a second storage capacity smaller than the first storage capacity.

9 . A method of manufacturing a semiconductor product, the method comprising:
providing a first semiconductor chip; forming a first interconnection structure on a first bonding pad on a first surface of the first semiconductor chip; providing a second semiconductor chip comprising a first surface comprising a bonding pad on which a second interconnection structure is formed; coupling the second interconnection structure to a second bonding pad on the first surface of the first semiconductor chip; encapsulating at least the first surface of the first semiconductor chip with an encapsulating material so that the second semiconductor chip and the first interconnection structure are encapsulated; removing a portion of the encapsulating material to expose a portion of the first interconnection structure; forming a conductive layer over a surface of the encapsulating material to electrically couple the conductive layer to the exposed first interconnection structure; and forming a third interconnection structure coupled to the conductive layer.

10 . The method of claim 9 , wherein the second bonding pad is located in a central region of the first surface of the first semiconductor chip, and the first bonding pad is located in a peripheral region of the first surface of the first semiconductor chip outside of the central region.

11 . The method of claim 9 , wherein said providing the first semiconductor chip comprises providing the first semiconductor chip in a wafer, and further comprising, after at least said forming a conductive layer, singulating the first semiconductor chip from the wafer.

12 . The method of claim 9 , wherein the first surface of the first semiconductor chip has a surface area of a first size and the first surface of the second semiconductor chip has a surface area that is smaller than the surface area of the first surface of the first semiconductor chip.

13 . The method of claim 9 , wherein corresponding edges of the first surface and the second surface of the first semiconductor chip are connected by side surfaces, and wherein the encapsulating material encapsulates the side surfaces of the first semiconductor chip.

14 . A semiconductor product, comprising:
a first semiconductor chip comprising a first surface and a second surface opposite the first surface of the first semiconductor chip; a first interconnection structure formed on a first bonding pad on the first surface of the first semiconductor chip; a second semiconductor chip comprising a first surface and a second surface opposite the first surface of the second semiconductor chip, the first surface of the second semiconductor chip comprising a bonding pad onto which is formed a second interconnection structure that electrically interconnects the second semiconductor chip to a second bonding pad on the first surface of the first semiconductor chip; an encapsulating material encapsulating at least the first surface of the first semiconductor chip and the first interconnection structure; a conductive layer electrically coupled to the first interconnection structure at a surface of the encapsulating material; a substrate coupled to the second surface of the first semiconductor chip; and a third interconnection structure coupled to the conductive layer.

15 . The semiconductor product of claim 14 , wherein the surface area of the first surface of the first semiconductor chip is larger than the surface area of the first surface of the second semiconductor chip.

16 . The semiconductor product of claim 14 , wherein the second bonding pad is located in a central region of the first surface of the first semiconductor chip, and the first bonding pad is located in a peripheral region of the first surface of the first semiconductor chip outside of the central region.

17 . The semiconductor product of claim 14 , wherein the first interconnection structure comprises a conductive pillar, the substrate is coupled to the second surface of the first semiconductor chip using an adhesive, and the substrate comprises one of a silicon material, a glass, and a metal.

18 . The semiconductor product of claim 14 , wherein the third interconnection structure comprises a solder ball.

19 . The semiconductor product of claim 14 , wherein side surfaces of the substrate, the encapsulating material, and a redistribution layer are coplanar.

20 . The semiconductor product of claim 14 , wherein the first semiconductor chip comprises a memory device of a first storage capacity, and the second semiconductor chip comprises a memory device of a second storage capacity smaller than the first storage capacity.

Assignees

• Amkor Technology Inc

Inventors

• Ko Yeong Beom
• Kim Dong Jin
• Cha Se Woong

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W72/073

  of die-attach connectors · CPC title

• H10W70/099

  Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers · CPC title

• H10W72/072

  of bump connectors · CPC title