Semiconductor device manufacturing method and semiconductor device manufactured using the same
US-2024395745-A1 · Nov 28, 2024 · US
by plating, e.g. electroless plating or electroplating
by plating, e.g. electroless plating or electroplating · Cooperative Patent Classification (CPC)
Electric circuits, power, telecommunications, and semiconductors.
Related technology areas
Mapped technology topics for this CPC code.
| Metric | Value |
|---|---|
| CPC code | H10W72/01935 |
| Official title | {by plating, e.g. electroless plating or electroplating} |
| Display label | by plating, e.g. electroless plating or electroplating |
| Total patents | 3,291 |
Filing trend
Year-over-year patent counts classified under this CPC code.
Filing activity over the last five years is declining.
| Year | Patents |
|---|---|
| 2015 | 314 |
| 2016 | 296 |
| 2017 | 342 |
| 2018 | 307 |
| 2019 | 288 |
| 2020 | 346 |
| 2021 | 364 |
| 2022 | 310 |
| 2023 | 241 |
| 2024 | 238 |
| 2025 | 211 |
| 2026 | 34 |
Representative patents
Representative publications under this CPC code from precomputed stats, or recent filings when stats are unavailable.
Microelectronic assemblies with inductors in direct bonding regions
US-2024355768-A1 · Oct 24, 2024 · US
Conductive barrier direct hybrid bonding
US-2024243085-A1 · Jul 18, 2024 · US
Chip package structure and method for preparing chip package structure
US-2024178167-A1 · May 30, 2024 · US
Wafer-level package including under bump metal layer
US-11862589-B2 · Jan 2, 2024 · US
Multiple bond via arrays of different wire heights on a same substrate
US-2015380377-A1 · Dec 31, 2015 · US
Semiconductor Device and Method of Forming Conductive Vias by Direct Via Reveal with Organic Passivation
US-2015380310-A1 · Dec 31, 2015 · US
Process for realizing a connecting structure
US-9224704-B2 · Dec 29, 2015 · US
Integrated inductor
US-9219106-B2 · Dec 22, 2015 · US
Conductive Line System and Process
US-2015364369-A1 · Dec 17, 2015 · US
Electronic device packages having bumps and methods of manufacturing the same
US-9209146-B2 · Dec 8, 2015 · US
Semiconductor package having heat dissipating member
US-2015348863-A1 · Dec 3, 2015 · US
Method of forming a semiconductor component comprising a second passivation layer having a first opening exposing a bond pad and a plurality of second openings exposing a top surface of an underlying first passivation layer
US-2015348922-A1 · Dec 3, 2015 · US
Semiconductor device and method of forming RDL over contact pad with high alignment tolerance or reduced interconnect pitch
US-9202713-B2 · Dec 1, 2015 · US
Semiconductor Device Having Solderable and Bondable Electrical Contact Pads
US-2015333023-A1 · Nov 19, 2015 · US
Semiconductor device and method for manufacturing the same
US-2015333024-A1 · Nov 19, 2015 · US
Articles including bonded metal structures and methods of preparing the same
US-2015333035-A1 · Nov 19, 2015 · US
Electroplated solder with eutectic chemical composition
US-2015318254-A1 · Nov 5, 2015 · US
Semiconductor chip having different conductive pad widths and method of making layout for same
US-2015318249-A1 · Nov 5, 2015 · US
Interconnect structures for stacked dies, including penetrating structures for through-silicon vias, and associated systems and methods
US-9165888-B2 · Oct 20, 2015 · US
Frequently asked questions
Answers are generated from the same data shown on this page.
- What is CPC H10W72/01935?
- CPC H10W72/01935 is the Cooperative Patent Classification code for “by plating, e.g. electroless plating or electroplating.”
- How many patents are filed under CPC H10W72/01935 (by plating, e.g. electroless plating or electroplating)?
- Our database includes 3,291 publications tagged with this CPC code.
- Is patent activity under CPC H10W72/01935 growing?
- Publication counts under this code: 238 in 2024 vs 211 in 2025 (latest complete years).