Semiconductor device and method of manufacturing semiconductor device

Patent metadata

Field	Value
Publication number	US-11646263-B2
Application number	US-202117155126-A
Country	US
Kind code	B2
Filing date	Jan 22, 2021
Priority date	Jun 11, 2020
Publication date	May 9, 2023
Grant date	May 9, 2023

Abstract

A semiconductor device includes a first insulating layer disposed on a substrate, a first wiring disposed in the first insulating layer, a first insulating barrier layer disposed on the first insulating layer, an etch-stop layer disposed on the first insulating barrier layer and having an area smaller than an area of the first insulating barrier layer in a plan view, a resistive metal pattern disposed on the etch-stop layer, a second insulating barrier layer disposed on the resistive metal pattern, a second insulating layer covering the first and second insulating barrier layers, a second wiring disposed in the second insulating layer, and a first conductive via disposed between the resistive metal pattern and the second wiring to penetrate through the second insulating barrier layer and the second insulating layer and electrically connect the resistive metal pattern and the second wiring.

First claim

What is claimed is:

1. A semiconductor device comprising:
a first insulating layer disposed on a substrate;
a first wiring disposed in the first insulating layer;
a first insulating barrier layer disposed on the first insulating layer;
an etch-stop layer disposed on the first insulating barrier layer and having a planar area smaller than a planar area of the first insulating barrier layer;
a resistive metal pattern disposed on the etch-stop layer;
a second insulating barrier layer disposed on the resistive metal pattern;
a second insulating layer covering the first insulating barrier layer and the second insulating barrier layer;
a second wiring disposed in the second insulating layer; and
a first conductive via disposed between the resistive metal pattern and the second wiring to penetrate through the second insulating barrier layer and the second insulating layer and electrically connect the resistive metal pattern and the second wiring.

2. The semiconductor device of claim 1 , wherein a lower surface of the etch-stop layer contacts an upper surface of the first insulating barrier layer, and an upper surface of the etch-stop layer contacts a lower surface of the resistive metal pattern.

3. The semiconductor device of claim 1 , wherein the etch-stop layer comprises a metal oxide containing aluminum (Al).

4. The semiconductor device of claim 3 , wherein the etch-stop layer further comprises at least one of nitrogen (N), carbon (C), zirconium (Zr), ruthenium (Ru), lanthanum (La), and hafnium (Hf).

5. The semiconductor device of claim 1 , wherein the second wiring has a region in which a thickness in a vertical direction of the second wiring decreases in a horizontal direction approaching the first conductive via.

6. The semiconductor device of claim 1 , wherein the second insulating layer covers side surfaces of the etch-stop layer, the resistive metal pattern, and the second insulating barrier layer.

7. The semiconductor device of claim 1 , wherein the second insulating layer has a first surface in contact with a lower surface of the second wiring, and
the first surface of the second insulating layer has a curved region above a side surface of the etch-stop layer.

8. The semiconductor device of claim 1 , wherein the first insulating barrier layer has a first thickness in a vertical direction,
the etch-stop layer has a second thickness in the vertical direction less than the first thickness, and
the resistive metal pattern has a third thickness in the vertical direction that is less than the first thickness and greater than the second thickness.

9. The semiconductor device of claim 1 , wherein each of a thickness of the first insulating barrier layer and a thickness of the second insulating barrier layer in a vertical direction is less than about 100 Å,
a thickness of the etch-stop layer in the vertical direction is less than about 30 Å, and
a thickness of the resistive metal pattern in the vertical direction is less than about 45 Å.

10. The semiconductor device of claim 1 , wherein the etch-stop layer covers an upper surface of the first insulating barrier layer, a side surface of the resistive metal pattern, and a side surface and an upper surface of the second insulating barrier layer.

11. The semiconductor device of claim 1 , wherein the second wiring extends in a first direction, and
the first wiring extends in a second direction perpendicular to the first direction.

12. The semiconductor device of claim 1 , wherein at least one of the first and second insulating barrier layers comprises two or more layers stacked in a vertical direction.

13. The semiconductor device of claim 1 , further comprising a capping layer covering an upper surface of the first wiring, between the first wiring and the first insulating barrier layer.

14. A semiconductor device comprising:
a first wiring disposed on a substrate;
a first insulating barrier layer disposed on the first wiring;
a resistive structure disposed on the first insulating barrier layer and including a resistive metal pattern;
an insulating layer disposed on the resistive structure;
a second wiring disposed in the insulating layer; and
a first conductive via penetrating through the insulating layer and electrically connecting the second wiring and the resistive metal pattern,
wherein the resistive structure includes,
an etch-stop layer disposed between the first insulating barrier layer and the resistive metal pattern, having an area smaller than an area of the first insulating barrier layer in a plan view, and having a thickness in a vertical direction less than a thickness of the resistive metal pattern in the vertical direction; and
a second insulating barrier layer disposed on the resistive metal pattern and penetrated by the first conductive via.

15. The semiconductor device of claim 14 , wherein a lower surface of the etch-stop layer contacts an upper surface of the first insulating barrier layer, and an upper surface of the etch-stop layer contacts a lower surface of the resistive metal pattern.

Assignees

• Samsung Electronics Co Ltd

Inventors

• You Wookyung
• Park Kyeongbeom
• Park Sungbin
• Park Suhyun
• Baek Jongmin
• Lee Jangho
• Lim Seonghun
• Jung Deokyoung
• Han Kyuhee

Classifications

• H10W20/498 Primary

  Resistive arrangements or effects of, or between, wiring layers · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/47

  comprising two or more dielectric layers having different properties, e.g. different dielectric constants · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/42 Primary

  Vias, e.g. via plugs · CPC title