Semiconductor devices and methods of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9728490-B2
Application number	US-201615151079-A
Country	US
Kind code	B2
Filing date	May 10, 2016
Priority date	Aug 24, 2015
Publication date	Aug 8, 2017
Grant date	Aug 8, 2017

Abstract

A semiconductor device includes a via structure penetrating through a substrate, a portion of the via structure being exposed over a surface of the substrate, a protection layer pattern structure provided on the surface of the substrate and including a first protection layer pattern and a second protection layer pattern, the first protection layer pattern surrounding a lower sidewall of the exposed portion of the via structure and exposing an upper sidewall of the exposed portion of the via structure, the second protection layer pattern exposing a portion of the top surface of the first protection layer pattern adjacent to the sidewall of the via structure, and a pad structure provided on the via structure and the protection layer pattern structure and covering the top surface of the first protection layer pattern exposed by the second protection layer pattern.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate;
a via structure in the substrate, wherein a portion of the via structure extends past a surface of the substrate;
a protection layer pattern structure on the surface of the substrate, wherein the protection layer pattern includes a first protection layer pattern and a second protection layer pattern on the first protection layer pattern, the first protection layer pattern surrounding a lower sidewall of a protruding portion of the via structure from the surface of the substrate, the second protection layer pattern being spaced apart from the protruding portion of the via structure by a predetermined distance;
a pad structure on the via structure and the protection layer pattern structure, wherein the pad structure covers a portion of a top surface of the first protection layer pattern; and
a seed pattern disposed between the via structure and the pad structure, between the top surface of the first protection layer pattern and the pad structure, or between the second protection layer pattern and the pad structure,
wherein the pad structure laterally overlaps the first and second protection layer patterns by a first distance and the seed pattern laterally overlaps the first and second protection layer patterns by a second distance that is less than the first distance, and
wherein the via structure comprises:
a via hole in the substrate;
a via electrode in the via hole, the via electrode including a conductive pattern and a barrier pattern on a sidewall of the conductive pattern; and
an insulation layer pattern in the via hole surrounding the via electrode, wherein the insulation layer pattern is between the via electrode and the substrate.

2. The semiconductor device of claim 1 , wherein a top surface of the insulation layer pattern is lower than a top surface of the via electrode.

3. The semiconductor device of claim 1 , wherein the conductive pattern comprises a metal, the barrier pattern comprises a metal nitride and the insulation layer pattern comprises silicon nitride.

4. The semiconductor device of claim 1 , wherein the first protection layer pattern has an etch selectivity that is different from an etch selectivity of the second protection layer pattern.

5. The semiconductor device of claim 1 , wherein the first protection layer pattern comprises silicon oxide and the second protection layer pattern comprises silicon nitride.

6. The semiconductor device of claim 1 , wherein the top surface of the portion of the first protection layer pattern that is exposed by the second protection layer pattern is lower than a top surface of the via structure.

7. The semiconductor device of claim 6 , wherein the top surface of the portion of the first protection layer pattern that is exposed by the second protection layer pattern is higher than a bottom surface of the second protection layer pattern.

8. The semiconductor device of claim 1 , wherein a bottom surface of the seed pattern has an uneven structure corresponding to height variations of the via structure and the protection layer pattern structure.

9. The semiconductor device of claim 1 , wherein the seed pattern has a flat upper surface.

10. The semiconductor device of claim 1 , wherein a width of the seed pattern is less than a width of the pad structure.

11. The semiconductor device of claim 1 , wherein the pad structure comprises copper.

12. The semiconductor device of claim 1 , wherein the pad structure comprises a lower pad on the seed pattern and an upper pad on the lower pad opposite the seed pattern.

13. The semiconductor device of claim 12 , wherein the lower pad comprises nickel, and the upper pad comprises gold.

14. A semiconductor device, comprising:
a substrate;
a conductive plug in the substrate, wherein a protruding portion of the conductive plug protrudes from a surface of the substrate;
a first protection layer pattern on the surface of the substrate, wherein the first protection layer pattern contacts a lower sidewall of the protruding portion of the conductive plug that extends past the surface of the substrate;
a second protection layer pattern on the first protection layer pattern opposite the substrate, wherein a sidewall of the second protection layer pattern is spaced apart from the conductive plug, and wherein the first protection layer pattern and the second protection layer pattern define a recess adjacent an upper portion of an exposed sidewall of the conductive plug;
a pad structure on the conductive plug, the first protection layer pattern and the second protection layer pattern, wherein the pad structure extends into the recess; and
a seed layer between the conductive plug and the pad structure, between the first protection layer pattern and the pad structure, or between the second protection layer pattern and the pad structure,
wherein the pad structure laterally overlaps the first and second protection layer patterns by a first distance and the seed layer laterally overlaps the first and second protection layer patterns by a second distance that is less than the first distance.

15. The semiconductor device of claim 14 , wherein the first protection layer pattern comprises a first portion adjacent the conductive plug and a second portion that is spaced apart laterally from the conductive plug by the first portion of the first protection layer pattern, wherein the first portion of the first protection layer pattern is thicker than the second portion of the first protection layer pattern.

16. A semiconductor device, comprising:
a substrate;
a conductive plug in the substrate, wherein a portion of the conductive plug protrudes from a surface of the substrate;
a first protection layer pattern on the surface of the substrate, wherein the first protection layer pattern contacts a lower portion of an exposed sidewall of the conductive plug that extends past the surface of the substrate;
a second protection layer pattern on the first protection layer pattern opposite the substrate, wherein a sidewall of the second protection layer pattern is spaced apart from the conductive plug and exposes an upper portion of the exposed sidewall of the conductive plug, and wherein the first protection layer and the second protection layer define a recess;
a pad structure on the conductive plug, the first protection layer pattern and the second protection layer pattern, wherein the pad structure extends into the recess;
an insulation layer pattern adjacent the conductive plug, wherein the insulation layer pattern extends above the substrate by a first distance and the conductive plug extends above the substrate by a second distance that is greater than the first distance; and
a seed layer disposed between the conductive plug and the pad structure between the first protection layer pattern and the pad structure, or between the second protection layer pattern and the pad structure,
wherein the pad structure laterally overlaps the first and second protection layer patterns by a third distance and the seed layer laterally overlaps the first and second protection layer patterns by a fourth distance that is less than the third distance.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Choi Ju-Il
• Kim Hyo-Ju
• Park Yeun-Sang
• Fujisaki Atsushi
• Moon Kwang-Jin
• Park Byung-Lyul

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W72/9415

  relative to the surface, e.g. recessed, protruding · CPC title

• H10W72/07254

  changes in dispositions · CPC title

• H10W72/07252

  changes in structures or sizes · CPC title