Semiconductor device and method for manufacturing semiconductor device

Patent metadata

Field	Value
Publication number	US-10707242-B2
Application number	US-201816200157-A
Country	US
Kind code	B2
Filing date	Nov 26, 2018
Priority date	Jun 10, 2016
Publication date	Jul 7, 2020
Grant date	Jul 7, 2020

Abstract

According to one embodiment, a semiconductor device includes an insulating substrate, a first semiconductor layer located above the insulating substrate, a second semiconductor layer located above the insulating substrate, an insulating layer which covers the first semiconductor layer and the second semiconductor layer, and includes a first contact hole reaching the first semiconductor layer and a second contact hole reaching the second semiconductor layer, a barrier layer which covers one of the first semiconductor layer inside the first contact hole and the second semiconductor layer inside the second contact hole, and a first conductive layer which is in contact with the barrier layer.

First claim

What is claimed is:

1. An array substrate comprising:
an insulating substrate;
a first semiconductor layer located above the insulating substrate;
a first insulating layer located above the first semiconductor layer;
a second semiconductor layer located above the first insulating layer;
a second insulating layer located above the second semiconductor layer;
a first contact hole penetrating the first insulating layer and the second insulating layer, and reaching the first semiconductor layer;
a second contact hole penetrating the second insulating layer, and reaching the second semiconductor layer;
a barrier layer which is in contact with the second semiconductor layer in the second contact hole, and is conductive;
a first conductive layer which is connected to the first semiconductor layer in the first contact hole; and
a second conductive layer which is formed of a same material as a material of the first conductive layer and is connected to the barrier layer in the second contact hole.

2. The array substrate of claim 1 , further comprising:
a first gate electrode facing a top surface of the first semiconductor layer; and
a second gate electrode facing a top surface of the second semiconductor layer.

3. The array substrate of claim 1 , further comprising:
a metal layer facing a bottom surface of the second semiconductor layer.

4. The array substrate of claim 1 , wherein
the first semiconductor layer is formed of a polycrystalline silicon; and
the second semiconductor layer is formed of an oxide semiconductor.

5. The array substrate of claim 1 , wherein
the barrier layer is formed of a conductive metal material resistant to hydrofluoric acid.

6. The array substrate of claim 1 , wherein
the barrier layer is formed of titanium; and
the second conductive layer has a multilayer structure of titanium/aluminum/titanium.

Assignees

• Japan Display Inc

Inventors

• Hanada Akihiro
• Fuchi Masayoshi

Classifications

• H10P70/234

  the processing being the formation of vias or contact holes · CPC title

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/081

  by forming openings in the dielectric parts · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title