Semiconductor device having a lead flank and method of manufacturing a semiconductor device having a lead flank

Patent metadata

Field	Value
Publication number	US-11646248-B2
Application number	US-202217700962-A
Country	US
Kind code	B2
Filing date	Mar 22, 2022
Priority date	Jun 11, 2019
Publication date	May 9, 2023
Grant date	May 9, 2023

Abstract

A semiconductor device comprises a substrate having a substrate top side, a substrate lateral side, and a substrate bottom side, an electronic device on the substrate top side, and an encapsulant on the substrate top side and contacting a lateral surface of the electronic device. The substrate comprises a conductive structure and a dielectric structure that extends comprising a protrusion in contact with the encapsulant. The conductive structure comprises a lead comprising a lead flank, the lead flank comprising a cavity and a conductive coating on a surface of the lead in the cavity. The conductive structure comprises a pad exposed at the substrate top side, embedded in the dielectric structure, and adjacent to the protrusion, to electrically couple with the electronic device via a first internal interconnect. Other examples and related methods are also disclosed herein.

First claim

What is claimed is:

1. A method to manufacture a semiconductor device, comprising:
forming a pad and a lead on a top side of a conductive layer;
forming a dielectric structure on the top side of the conductive layer, wherein the dielectric structure covers the pad and the lead;
thinning the dielectric structure until the lead is exposed;
etching the lead so that a surface of the lead is depressed relative to a surface of the dielectric structure;
forming a cavity in the lead adjacent to the dielectric structure;
forming a plating layer on the lead, including on a portion of the lead in the cavity, to define a wettable flank of the lead in the cavity; and
etching a bottom side of the conductive layer so that a protrusion of the dielectric structure protrudes beyond a bottom of the pad.

2. The method of claim 1 , further comprising:
placing an electronic device on the bottom side of the conductive layer to couple the electronic device to the pad; and
forming an encapsulant over the electronic device, wherein the encapsulant contacts a lateral side of the electronic device and the protrusion of the dielectric structure extends into the encapsulant.

3. The method of claim 1 , further comprising:
forming a paddle on the top side of the conductive layer when the lead is formed
wherein forming the lead comprises plating a lead body on the conductive layer.

4. The method of claim 1 , wherein said thinning the dielectric structure comprises grinding the dielectric structure.

5. The method of claim 1 , wherein forming the pad and the lead comprises:
forming the pad and a lead base of the lead on the conductive layer; and
plating a lead body on the lead base.

6. A method to manufacture a semiconductor device, comprising:
providing a conductive structure comprising a first side and a second side opposite to the first side;
providing a dielectric structure in adjacent to the first side of the conductive structure, wherein the dielectric structure comprises a protrusion and the conductive structure comprises a pad bounded by the protrusion and a lead adjacent to the dielectric structure;
etching the first side of the conductive structure such that a surface of the lead is depressed relative to a surface of the dielectric structure;
providing a cavity in the lead adjacent to the dielectric structure; and
providing a plating on the conductive structure to cover the lead, including covering a portion of the lead in the cavity, wherein the plated cavity defines a wettable flank of the lead.

7. The method of claim 6 , further comprising:
attaching an electronic device to the conductive structure, wherein the electronic device is electrically coupled with the pad via an internal interconnect; and
forming a molding compound to cover the electronic device, wherein the molding compound contacts a side surface of the electronic device, and wherein the protrusion of the dielectric structure extends into the molding compound.

8. The method of claim 6 , wherein providing the cavity comprises forming a first cavity surface perpendicular to a second cavity surface.

9. The method of claim 6 , wherein said providing the cavity comprises forming a dimple-shaped cavity surface.

10. The method of claim 7 , wherein:
the protrusion protrudes higher than a top surface of the pad; and
a bottom portion of the internal interconnect is bounded by the protrusion.

11. A method to manufacture a semiconductor device, comprising:
providing a conductive layer comprising a first side and a second side opposite to the first side;
providing a pad on the first side of the conductive layer;
providing a paddle on the first side of the conductive layer, and a lead on the first side of the conductive layer adjacent to the pad;
providing a dielectric structure on the first side of the conductive layer over the paddle and over the lead, wherein the dielectric structure comprises a protrusion adjacent to the pad;
removing a portion of the dielectric structure to expose the paddle and the lead;
providing a cavity in an exposed side of the lead; and
providing a plating layer in the cavity of the lead.

12. The method of claim 11 , wherein:
a side of the dielectric structure is coplanar with an exposed side of the paddle and the exposed side of the lead after removing the portion of the dielectric structure.

13. The method of claim 11 , comprising:
removing a portion of the lead at the exposed side of the lead;
wherein an exposed side of the dielectric structure protrudes above the exposed side of the lead.

14. The method of claim 11 , wherein a surface of the plating layer protrudes past an exposed side of the dielectric structure.

15. The method of claim 11 , wherein a surface of the plating layer is substantially coplanar with an exposed side of the dielectric structure.

16. The method of claim 11 , wherein the conductive layer comprises a copper foil.

17. The method of claim 11 , wherein the cavity is formed via etching the first side of the conductive layer.

18. The method of claim 11 , wherein the paddle and the lead are formed via a plating process.

19. The method of claim 1 , wherein:
the conductive layer is formed on a carrier; and
removing the carrier prior to etching the bottom side of the conductive layer.

20. The method of claim 5 , comprising:
forming a paddle base on the conductive layer when the lead base is formed; and
plating a paddle body on the paddle base when the lead body is plated.

Assignees

• Amkor Tech Singapore Holding Pte Ltd

Inventors

• Bang Won Bae
• Oh Kwang Seok
• Scott George

Classifications

• H10W72/551

  Materials of bond wires · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/0198 Primary

  batch processes · CPC title

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title