Method of forming a packaged semiconductor device having enhanced wettable flank and structure

US10529655B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10529655-B2
Application numberUS-201816229077-A
CountryUS
Kind codeB2
Filing dateDec 21, 2018
Priority dateSep 9, 2017
Publication dateJan 7, 2020
Grant dateJan 7, 2020

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

A packaged electronic device includes a substrate having a lead. The lead includes an outward facing side surface having a first height, and an inward facing side surface having a second height that is less than the first height. An electronic device is electrically connected to the lead. A package body encapsulates the electronic device and portions of the lead. The outward facing side surface is exposed through a side surface of the package body, and the inward facing side surface is encapsulated by the package body. A conductive layer is disposed on the outward facing side surface to provide the packaged electronic device with an enhanced wettable flank. In one embodiment, the electronic device is electrically connected to a thick terminal portion having the outward facing side surface. In another embodiment, the electronic device is electrically connected to a thin terminal portion having the inward facing side surface.

First claim

Opening claim text (preview).

What is claimed is: 1. A packaged electronic device comprising: a substrate comprising: a conductive pattern layer; a conductive pillar layer disposed on a first portion of the conductive pattern layer, wherein: the conductive pillar layer and the first portion of conductive pattern layer provide a first terminal portion and a second portion of the conductive pattern layer provides a second terminal portion; the first terminal portion and the second terminal portion are configured as a lead; the first terminal portion comprises a first thickness; the second terminal portion comprises an inward facing side surface having a second thickness that is less than the first thickness; and the first terminal portion comprises an outward facing side surface of the lead; an electronic device electrically coupled to the lead; a package body encapsulating the electronic device; and a conductive layer disposed on the outward facing side surface of the lead. 2. The packaged electronic device of claim 1 , wherein: the conductive pattern layer further comprises a pad; and the electronic device is disposed adjacent to the pad. 3. The packaged electronic device of claim 2 , wherein: the conductive layer is disposed on a surface of the pad; and the conductive layer is disposed on a surface of the second terminal portion. 4. The packaged electronic device of claim 1 , wherein: the second terminal portion is provided absent the conductive pillar layer; the outward facing side surface of the lead comprises an outward facing recessed side surface; and the conductive layer is disposed on a vertical portion of the outward facing recessed side surface. 5. The packaged electronic device of claim 4 , wherein: the conductive layer is disposed on a horizontal portion of the outward facing recessed surface. 6. The packaged electronic device of claim 1 , wherein: the substrate further comprises a molded layer covering portions of the conductive pillar layer and at least portions of the second portion of the conductive pattern layer; a portion of the package body physically contacts at least a portion of an upper surface of the molded layer; and the conductive pillar layer comprises a bottom surface exposed to the outside of the molded layer. 7. The packaged electronic device of claim 6 , wherein: the conductive pattern layer is recessed below the upper surface of the molded layer. 8. The packaged electronic device of claim 1 , wherein: the substrate further comprises a molded layer covering portions of the conductive pillar layer and at least portions of the second portion of the conductive pattern layer; and the outward facing side surface of the lead is exposed in a side surface of the molded layer. 9. A packaged electronic device comprising: a substrate comprising: a conductive pattern layer; a conductive pillar layer disposed on a first portion of the conductive pattern layer, wherein: the conductive pillar layer and the first portion of the conductive pattern layer provide a first terminal portion and a second portion of the conductive pattern layer provides a second terminal portion; the first terminal portion and the second terminal portion are configured as a lead; the first terminal portion comprises an outward facing side surface of the lead; and a molded layer covering portions of the conductive pillar layer and at least portions of the second portion of the conductive pattern layer; an electronic device electrically coupled to the lead; a package body encapsulating the electronic device; and a conductive layer disposed on the outward facing side surface of the lead. 10. The packaged electronic device of claim 9 , wherein: the first terminal portion comprises a first thickness; and the second terminal portion comprises an inward facing side surface having a second thickness that is less than the first thickness. 11. The packaged electronic device of claim 9 , wherein: the conductive pillar layer has a thickness that is greater than that of the conductive pattern layer. 12. The packaged electronic device of claim 9 , wherein: the conductive pattern layer further comprises a pad; the electronic device is disposed adjacent to the pad; and the pad is provided absent the conductive layer. 13. The packaged electronic device of claim 9 , wherein: the second terminal portion and the conductive pillar layer do not overlap in a cross-sectional view; and the outward facing side surface of the lead comprises an outward facing recessed side surface exposed in a side surface of the molded layer. 14. The packaged electronic device of claim 9 , wherein: the electronic device is attached to the conductive pattern layer with a conductive bump in a flip-chip configuration. 15. A method of forming a packaged electronic device, comprising: providing a substrate comprising: a lead comprising: a first terminal portion having a first thickness; and a second terminal portion having an inward facing side surface and having a second thickness that is less than the first thickness; removing a first portion of the first terminal portion to provide the first terminal portion with a first outward facing side surface of the lead while leaving a second portion of the first terminal portion intact; forming a conductive layer on the first outward facing side surface of the lead; electrically coupling an electronic device to the lead; providing a package body encapsulating the electronic device and portions of the lead; and singulating the second portion of the first terminal portion and the package body to provide the first terminal portion with a second outward facing side surface that is offset from the first outward facing side surface, wherein the second terminal portion remains intact as part of the packaged electronic device. 16. The method of claim 15 , wherein: both removing the first portion of the terminal portion and forming the conductive layer occur after electrically coupling the electronic device to the lead and after forming the package body; forming the conductive layer comprises: plating the conductive layer; and using the second portion of the first terminal portion as an electrical path for the plating step. 17. The method of claim 15 , wherein: providing the substrate comprises providing the inward facing side surface comprising a portion that is recessed inward. 18. The method of claim 15 , wherein: removing the first portion of the first terminal portion comprises partially sawing into the first terminal portion; and singulating comprises leaving part of the second portion of the first terminal portion intact as part of the packaged electronic device. 19. The method of claim 15 , wherein: providing the substrate comprises providing the substrate having a pad; the method further comprises attaching the electronic device to the pad; electrically coupling the electronic device to the lead comprises using a conductive connective structure attached to the electronic device and attached the lead. 20. The method of claim 19 , wherein: electrically coupling the electronic device comprises physically attaching the conductive connective structure directly to the first terminal portion. 21. The method of claim 15 , wherein providing the substrate comprises: providing a conductive substrate having a first major surface and a second major surface opposite to the first major surface, wherein the conductive substrate ha

Assignees

Inventors

Classifications

  • between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

  • between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

  • between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

  • the encapsulations exposing the passive side of the semiconductor body · CPC title

  • the semiconductor body being completely enclosed · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US10529655B2 cover?
A packaged electronic device includes a substrate having a lead. The lead includes an outward facing side surface having a first height, and an inward facing side surface having a second height that is less than the first height. An electronic device is electrically connected to the lead. A package body encapsulates the electronic device and portions of the lead. The outward facing side surface…
Who is the assignee on this patent?
Amkor Technology Inc
What technology area does this patent fall under?
Primary CPC classification H10W72/072. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jan 07 2020 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).