Dynamic gate-overdrive voltage boost receiver

Patent metadata

Field	Value
Publication number	US-11637356-B1
Application number	US-202217649526-A
Country	US
Kind code	B1
Filing date	Jan 31, 2022
Priority date	Jan 31, 2022
Publication date	Apr 25, 2023
Grant date	Apr 25, 2023

Abstract

In certain aspects, a receiving circuit includes a splitter, a first receiver, a second receiver, and a boost circuit. The splitter is configured to receive an input signal, split the input signal into a first signal and a second signal, output the first signal to the first receiver, and output the second signal to the second receiver. In certain aspects, the voltage swing of the input signal is split between the first signal and the second signal. The boost circuit may be configured to shift a supply voltage of the second receiver to boost a gate-overdrive voltage of a transistor in the second receiver during a transition of the input signal (e.g., transition from low to high). In certain aspects, the boost circuit controls the gate-overdrive voltage boosting based on the first signal and the second signal.

First claim

What is claimed is:

1. A receiving circuit, comprising:
a splitter having a first output and a second output, wherein the splitter is configured to receive an input signal, split the input signal into a first signal and a second signal, output the first signal at the first output, and output the second signal at the second output;
a first receiver having an input and an output, wherein the input of the first receiver is coupled to the first output of the splitter;
a second receiver having an input and an output, wherein the input of the second receiver is coupled to the second output of the splitter; and
a first boost circuit having a first input, a second input, and an output, wherein the first input of the first boost circuit is coupled to the input of the first receiver, the second input of the first boost circuit is coupled to the input of the second receiver, and the output of the first boost circuit is coupled to a supply terminal of the second receiver.

2. The receiving circuit of claim 1 , wherein the first boost circuit is configured to shift a supply voltage of the second receiver based on the first signal and the second signal.

3. The receiving circuit of claim 2 , wherein the first boost circuit is configured to shift the supply voltage of the second receiver during a transition of the input signal from low to high.

4. The receiving circuit of claim 2 , wherein the first boost circuit is configured to shift the supply voltage of the second receiver between a time that the first signal crosses a first threshold and a time that the second signal crosses a second threshold.

5. The receiving circuit of claim 2 , wherein the first boost circuit is configured to shift the supply voltage of the second receiver lower.

6. The receiving circuit of claim 1 , further comprising a second boost circuit having a first input, a second input, and an output, wherein the first input of the second boost circuit is coupled to the input of the first receiver, the second input of the second boost circuit is coupled to the input of the second receiver, and the output of the second boost circuit is coupled to a supply terminal of the first receiver.

7. The receiving circuit of claim 6 , wherein the second boost circuit is configured to shift a supply voltage of the first receiver based on the first signal and the second signal.

8. The receiving circuit of claim 7 , wherein the second boost circuit is configured to shift the supply voltage of the first receiver during a transition of the input signal from high to low.

9. The receiving circuit of claim 7 , wherein the second boost circuit is configured to shift the supply voltage of the first receiver between a time that the second signal crosses a first threshold and a time that the first signal crosses a second threshold.

10. The receiving circuit of claim 7 , wherein the second boost circuit is configured to shift the supply voltage of the first receiver higher.

11. The receiving circuit of claim 1 , further comprising a logic decision circuit having a first input, a second input, and an output, wherein the first input of the logic decision circuit is coupled to the output of the first receiver, and the second input of the logic decision circuit is coupled to the output of the second receiver.

12. The receiving circuit of claim 11 , wherein the logic decision circuit is configured to:
output a first logic value when both the first receiver and the second receiver output a logic zero; and
output a second logic value when both the first receiver and the second receiver output a logic one.

13. The receiving circuit of claim 1 , wherein the input signal has a first voltage swing, the first signal has a second voltage swing, the second signal has a third voltage swing, and each one of the second voltage swing and the third voltage swing is less than the first voltage swing.

14. A receiving circuit, comprising:
a splitter having a first output and a second output, wherein the splitter is configured to receive an input signal, split the input signal into a first signal and a second signal, output the first signal at the first output, and output the second signal at the second output;
a first receiver having an input and an output, wherein the input of the first receiver is coupled to the first output of the splitter;
a second receiver having an input and an output, wherein the input of the second receiver is coupled to the second output of the splitter;
a first boost circuit having a first input, a second input, and an output, wherein the first input of the first boost circuit is coupled to the input of the first receiver, the second input of the first boost circuit is coupled to the input of the second receiver, and the output of the first boost circuit is coupled to a supply terminal of the second receiver; and
a second boost circuit having a first input, a second input, and an output, wherein the first input of the second boost circuit is coupled to the input of the first receiver, the second input of the second boost circuit is coupled to the input of the second receiver, and the output of the second boost circuit is coupled to a supply terminal of the first receiver.

15. The receiving circuit of claim 14 , wherein:
the first boost circuit is configured to output a first supply voltage to the supply terminal of the second receiver, and to shift the first supply voltage based on the first signal and the second signal; and
the second boost circuit is configured to output a second supply voltage to the supply terminal of the first receiver, and to shift the second supply voltage based on the first signal and the second signal.

16. The receiving circuit of claim 15 , wherein:
the first boost circuit is configured to shift the first supply voltage during a transition of the input signal from low to high; and
the second boost circuit is configured to shift the second supply voltage during a transition of the input signal from high to low.

17. The receiving circuit of claim 15 , wherein:
the first boost circuit is configured to shift the first supply voltage between a time that the first signal crosses a first threshold and a time that the second signal crosses a second threshold; and
the second boost circuit is configured to shift the supply voltage of the second supply voltage between a time that the second signal crosses a third threshold and a time that the first signal crosses a fourth threshold.

18. The receiving circuit of claim 15 , wherein:
the first boost circuit is configured to shift the first supply voltage lower; and
the second boost circuit is configured to shift the second supply voltage higher.

19. The receiving circuit of claim 14 , further comprising a logic decision circuit having a first input, a second input, and an output, wherein the first input of the logic decision circuit is coupled to the output of the first receiver, and the second input of the logic decision circuit is coupled to the output of the second receiver.

20. The receiving circuit of claim 19 , wherein the logic decision circuit is configured to:
output a first logic value when both the first receiver and the second receiver output a logic zero; and
output a second logic value when both the first receiver and the second receiver output a logic one.

21. The receiving circuit of claim 14 , wherein the input signal has a first voltage swing, the first signal has a second voltage swing, the second signal has a third voltage swing, and each one of the second volt

Assignees

• Qualcomm Inc

Inventors

• Presswala Aliasgar
• Chen Wilson Jianbo
• Tan Chiew-Guan

Classifications

• H03K17/081

  without feedback from the output circuit to the control circuit · CPC title

• H03K19/0027

  in field effect transistor circuits · CPC title

• H03K19/00315 Primary

  in field-effect transistor circuits · CPC title

• H01P5/12 Primary

  Coupling devices having more than two ports (H01P5/04 takes precedence) · CPC title

• H02M3/155

  using semiconductor devices only · CPC title