Voltage level shifting with reduced timing degradation
US-11942933-B2 · Mar 26, 2024 · US
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Presswala Aliasgar patents
Presswala Aliasgar is listed as an inventor on 4 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Presswala Aliasgar |
| Total patents | 4 |
| First publication | Nov 9, 2021 |
| Latest publication | Mar 26, 2024 |
Notable patents
Publications ranked by popularity score, then publication date.
Voltage level shifting with reduced timing degradation
US-2023145180-A1 · May 11, 2023 · US
Dynamic gate-overdrive voltage boost receiver
US-11637356-B1 · Apr 25, 2023 · US
Static and intermittent dynamic multi-bias core for dual pad voltage level shifter
US-11171649-B1 · Nov 9, 2021 · US
Recent patents
Latest publications not already listed above.
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Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Qualcomm Inc | 4 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| H03K19/00315 | 3 |
| H03K19/018521 | 3 |
| H03K3/0375 | 2 |
| H03K17/081 | 1 |
| H03K19/0027 | 1 |