High voltage input receiver using low-voltage devices

Patent metadata

Field	Value
Publication number	US-9735763-B1
Application number	US-201615083030-A
Country	US
Kind code	B1
Filing date	Mar 28, 2016
Priority date	Mar 28, 2016
Publication date	Aug 15, 2017
Grant date	Aug 15, 2017

Abstract

An input receiver for stepping down a high power domain input signal for a high power domain powered by a high power supply voltage into an output signal for a low power domain includes a waveform splitter. The waveform splitter splits the high power domain input signal into a high voltage signal and a low voltage signal. A high voltage input receiver receives the high voltage signal to produce a received high voltage that is level shifted into a first input signal. A low voltage input receiver receives the low voltage signal to produce a second input signal. A logic circuit generates the output signal from the first input signal and the second input signal.

First claim

We claim:

1. A method of receiving a high power domain input signal for a high power domain powered by a high power supply voltage into an output signal for a low power domain powered by a low power supply voltage, comprising:
splitting the high power domain input signal with regard to the low power supply voltage into a high voltage signal that cycles between the low power supply voltage and the high power supply voltage and into a low voltage signal that cycles no greater than the low power supply voltage, wherein the high power supply voltage is greater than the low power supply voltage;
comparing the high voltage signal to a high threshold voltage that is greater than the low power supply voltage and less than the high power supply voltage to produce a received high voltage signal that cycles between the low power supply voltage and the high power supply voltage;
level shifting the received high voltage signal by the low power supply voltage into a first input signal for the low power domain;
comparing the low voltage signal to a low threshold voltage that is less than the low power supply voltage to produce a second input signal for the low power domain;
asserting an output signal for the low power domain to the low power supply voltage responsive to both the first input signal and the second input signal having a binary high state; and
discharging the output signal to ground responsive to both the first input signal and the second input signal having a binary zero state.

2. The method of claim 1 , wherein the high power domain is an I/O power domain and the high power supply voltage is an I/O power supply voltage, and wherein the low power domain is a core power domain and the low power supply voltage is a core power supply voltage.

3. The method of claim 1 , wherein the high power domain is a first I/O power domain and the high power supply voltage is a first I/O power supply voltage, and wherein the low power domain is a second I/O power domain and the low power supply voltage is a second I/O power supply voltage.

4. The method of claim 1 , wherein comparing the high voltage signal to the high threshold voltage to produce the received high voltage signal comprises passing the high voltage signal through an inverter.

5. The method of claim 3 , wherein the high threshold voltage substantially equals one half of a difference between the first I/O power supply voltage and the second I/O power supply voltage.

6. The method of claim 1 , wherein the low threshold voltage is less than the low power supply voltage and greater than 0 volts.

7. The method of claim 6 , wherein comparing the low voltage signal to the low threshold voltage to produce the second input signal comprises passing the low voltage signal through an inverter.

8. The method of claim 6 , wherein the low threshold voltage substantially equals one half of the low power supply voltage.

9. The method of claim 1 , wherein the low power domain output signal has a current binary value, the method further comprising:
latching the low power domain output signal at the current binary value responsive to the second input signal having a binary one value and the first input signal having a binary zero value.

10. The method of claim 1 , wherein splitting the high power domain input signal into the low voltage signal comprises:
passing the high power domain input signal through an NMOS pass transistor having its gate biased by the low power supply voltage to produce the low voltage signal; and
clamping the low voltage signal at the low power supply voltage while the high power domain input signal is greater than the low power supply voltage.

11. The method of claim 1 , wherein splitting the high power domain input signal into the high voltage signal comprises:
generating a bias voltage equal to the low power supply voltage when the first input signal and the second input signal both are in a binary one state;
lowering the bias voltage from the low power supply voltage responsive to the first input signal being in a binary zero state while the second input signal is in a binary one state;
passing the high power domain input signal through a PMOS pass transistor having its gate biased by the bias voltage to produce the high voltage signal; and
clamping the high voltage signal at the low power supply voltage while the high power domain input signal is less than the low power supply voltage.

12. An input receiver for receiving a high power domain input signal from a high power domain powered by a high power supply voltage, wherein the input receiver is within a low power domain powered by a low power supply voltage, comprising:
a waveform splitter configured to split the high power domain input signal into a high voltage signal that is greater than or equal to the low power supply voltage and into a low voltage signal that is less than or equal to the low power supply voltage, wherein the high power supply voltage is greater than the low power supply voltage;
a high voltage input receiver configured to compare the high voltage signal to a high voltage threshold that is greater than the low power supply voltage and less than the high power supply voltage to generate a received high voltage signal;
a level shifter configured to shift the received high voltage signal by the low power supply voltage to produce a first input signal for the low power domain;
a low voltage input receiver configured to compare the low voltage signal to a low voltage threshold that is less than the low power supply voltage to generate a second input signal for the low power domain; and
a logic circuit configured to charge an output signal for the low power domain to the low power supply voltage responsive to the first input signal and the second input signal both having a binary one state and configured to discharge the output signal to ground responsive to the first input signal and the second input signal both having a binary zero state.

13. The input receiver of claim 12 , wherein the high power domain is an I/O power domain and the high power supply voltage is an I/O power supply voltage, and wherein the low power domain is a core power domain and the low power supply voltage is a core power supply voltage.

14. The input receiver of claim 12 , wherein the high power domain is a first I/O power domain and the high power supply voltage is a first I/O power supply voltage, and wherein the low power domain is a second I/O power domain and the low power supply voltage is a second I/O power supply voltage.

15. The input receiver of claim 12 , wherein the high voltage input receiver comprises an inverter including a PMOS transistor in series with an NMOS transistor, and wherein a source of the NMOS transistor is coupled to a low power supply node for supplying the low power supply voltage and wherein a source of the PMOS transistor is coupled to a high power supply node for supplying the high power supply voltage.

16. The input receiver of claim 12 , wherein the low voltage input receiver comprises an inverter including a PMOS transistor in series with an NMOS transistor, and wherein a source of the NMOS transistor is coupled to ground and wherein a source of the PMOS transistor is coupled to a low power supply node for supplying the low power supply voltage.

17. The input receiver of claim 12 , wherein the logic circuit includes a latch for storing a current state of the output signal.

18. The input receiver of claim 17 , wherein the latch comprises a first inverter cross-coupled with a second inverter, and wherein the log

Assignees

• Qualcomm Inc

Inventors

• Chen Wilson
• Tan Chiew-Guan
• Rao Sumit

Classifications

• H03K5/08 Primary

  by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding (H03K5/07 takes precedence; comparing one pulse with another H03K5/22; providing a determined threshold for switching H03K17/30) · CPC title

• H03K19/00315

  in field-effect transistor circuits · CPC title

• H03K5/24

  the characteristic being amplitude · CPC title

• H03K3/3565

  Bistables with hysteresis, e.g. Schmitt trigger · CPC title

• H03K19/0175

  Coupling arrangements; Interface arrangements (interface arrangements for digital computers G06F3/00, G06F13/00) · CPC title