Semiconductor memory including plural memory blocks, a sequencer that controls a driver, a row decoder, and sense amplifier modules based on commands held in a command register to perform read, write, erase

Patent metadata

Field	Value
Publication number	US-10790025-B2
Application number	US-201916291163-A
Country	US
Kind code	B2
Filing date	Mar 4, 2019
Priority date	Jun 1, 2018
Publication date	Sep 29, 2020
Grant date	Sep 29, 2020

Abstract

According to one embodiment, a semiconductor memory includes: a memory cell array provided in a first layer above a semiconductor substrate and including a plurality of memory cells; a first word line coupled to a first memory cell of the plurality of memory cells; a driver generating a voltage applied to the first word line; a first transistor including one end coupled to the first word line and the other end coupled to the driver; a first transfer gate line coupled to a gate of the first transistor and including a portion passing through the first layer, a second layer between the semiconductor substrate and the first layer, and a third layer above the first layer; and a first level shifter applying a voltage to the first transfer gate line.

First claim

What is claimed is:

1. A semiconductor memory comprising:
a memory cell array in a first layer above a semiconductor substrate, the memory cell array including a plurality of memory cells;
a first word line coupled to a first memory cell included in the plurality of memory cells;
a driver generating a voltage applied to the first word line;
a first transistor including one end coupled to the first word line and the other end coupled to the driver;
a first transfer gate line coupled to a gate of the first transistor, the first transfer gate line including a portion passing through the first layer, a second layer between the semiconductor substrate and the first layer, and a third layer above the first layer;
a first level shifter applying a voltage to the first transfer gate line;
a second word line coupled to a second memory cell included in the memory cells;
a second transistor including one end coupled to the second word line and the other end coupled to the driver;
a second transfer gate line coupled to a gate of the second transistor;
a second level shifter applying a voltage to the second transfer gate line,
wherein a direction in which a region where a circuit corresponding to the first level shifter is provided and a region where a circuit corresponding to the second level shifter is provided are aligned is different from a direction in which the first transistor and the second transistor are aligned, and
the second transistor is arranged along a third side of a rectangular region where the memory cell array is provided, and the second level shifter is arranged along the third side of the rectangular region.

2. The memory of claim 1 , wherein
the first transfer gate line includes a portion extending in a first direction intersecting with an extending direction of the first word line.

3. The memory of claim 1 , further comprising:
a plurality of bit lines coupled to the memory cell array, each of the bit lines extending in a first direction; and
a sense amplifier module under the memory cell array, the sense amplifier module including a plurality of sense amplifiers respectively coupled to the bit lines,
wherein a dimension in the first direction of a rectangular region where the sense amplifier module is provided is equal to or larger than a half of a dimension in the first direction of a rectangular region where the memory cell array is provided.

4. The memory of claim 3 , wherein
a distance between the first transistor and the first level shifter is equal to or larger than a half of a length of the bit lines.

5. The memory of claim 3 , wherein
the sense amplifier module and the first transistor are adjacent.

6. The memory of claim 3 , wherein
the sense amplifier module includes a plurality of latch circuits.

7. The memory of claim 1 , wherein
the first transistor and the first level shifter are not arranged on a straight line along the extending direction of the first word line.

8. The memory of claim 1 , wherein
the first transistor is arranged along a first side of a rectangular region where the memory cell array is provided, and
the first level shifter is arranged along a second side different from the first side of the rectangular region.

9. The memory of claim 8 , wherein
the first transfer gate line intersects with the first side and the second side of the memory cell array.

10. The memory of claim 1 , wherein
the second transfer gate line includes no portion passing through the first layer.

11. The memory of claim 1 , wherein
the second transistor and the second level shifter are arranged on a straight line along an extending direction of the second word line.

12. The memory of claim 1 , wherein
the second transfer gate line intersects with the third side of the memory cell array, and does not intersect with a fourth side different from the third side of the rectangular region.

13. The memory of claim 1 , wherein
the first level shifter is provided on the semiconductor substrate, and
a region where the first level shifter is provided includes a portion arranged under the memory cell array.

14. The memory of claim 1 , wherein
the first level shifter is provided on the semiconductor substrate, and
a region where the first level shifter is provided includes no portion arranged under the memory cell array.

15. The memory of claim 1 , further comprising:
an address decoder coupled to the first level shifter,
wherein the memory cell array includes a plurality of blocks, and the address decoder controls the first level shifter in accordance with an inputted block address.

16. The memory of claim 1 , further comprising:
a plurality of conductive layers stacked via insulating layers; and
a pillar passing through the conductive layers,
wherein one conductive layer included in the conductive layers is used as the first word line, and
portions where the conductive layers and the pillar intersect function as memory cell transistors.

Assignees

• Toshiba Memory Corp

Inventors

• Yamaoka Masashi

Classifications

• G11C16/30 Primary

  Power supply circuits · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/08 Primary

  Address circuits; Decoders; Word-line control circuits · CPC title

• H01L27/1157

  Electricity · mapped topic