Glitch-free wide supply range transceiver for integrated circuits

Patent metadata

Field	Value
Publication number	US-10484041-B2
Application number	US-201715703800-A
Country	US
Kind code	B2
Filing date	Sep 13, 2017
Priority date	Sep 13, 2017
Publication date	Nov 19, 2019
Grant date	Nov 19, 2019

Abstract

An example receiver includes: a pad splitter circuit coupled to a pad, the pad splitter circuit configured to generate a first logic signal and a second logic signal; a wide-range receiver coupled to the pad splitter circuit to receive the first and second logic signals, the wide-range receiver comprising a combination of a first Schmitt trigger receiver and a second Schmitt trigger receiver; a control circuit coupled to the pad splitter circuit and the wide-range receiver; and a bias generator circuit coupled to the pad splitter circuit and the wide-range receiver.

First claim

What is claimed is:

1. A transmitter, comprising:
an input circuit configured to couple a logic signal to a first node and a second node;
a first level-shifter having an input coupled to the first node;
a first pre-driver having an input coupled to an output of the first level-shifter;
a second-level shifter having an input coupled to the second node, the second level-shifter is configured to perform a first level shift of the logic signal to generate a first logic signal and a second level shift of the logic signal to generate a second logic signal, and wherein an output of the second level-shifter includes the first logic signal and the second logic signal;
a second pre-driver having an input coupled to the output of the second level-shifter, the second pre-driver configured to generate an output signal having a first voltage swing in a first mode and a second voltage swing in a second mode, the second pre-driver comprising a stack of a first p-channel transistor, a second p-channel transistor, a first n-channel transistor, and a second n-channel transistor coupled between a supply node and a reference node, a gate of the first p-channel transistor receiving the first logic signal, a gate of the second n-channel transistor receiving the second logic signal, and gates of the second p-channel transistor and the first n-channel transistor receiving a first and second bias voltages, respectively; and
a driver including a stack of a top p-channel transistor, a bottom p-channel transistor, a top n-channel transistor, and a bottom n-channel transistor coupled between a the supply node and a ground node, a gate of the top p-channel transistor coupled to receive the output signal of the second pre-driver, a gate of the bottom n-channel transistor coupled to an output of the first pre-driver, and gates of the bottom p-channel transistor and the top n-channel transistor coupled to receive the first and second bias voltages, respectively.

2. The transmitter of claim 1 , wherein the second pre-driver comprises:
a third p-channel transistor and a third n-channel transistor coupled between the second p-channel transistor and the first n-channel transistor, a gate of the third p-channel transistor coupled to a source of the third n-channel transistor and a drain of the first n-channel transistor, a gate of the third n-channel transistor coupled to a source of the third p-channel transistor and a drain of the second p-channel transistor.

3. The transmitter of claim 1 , wherein the second pre-driver comprises:
a slew control circuit coupled between the second n-channel transistor and the reference node.

4. The transmitter of claim 1 , wherein the second pre-driver comprises:
a transmission gate coupled between the gate of the first p-channel transistor and a gate of the second n-channel transistor, the transmission gate including a first control terminal coupled to receive a first enable signal and a second control terminal coupled to receive a second enable signal.

5. The transmitter of claim 4 , wherein the second pre-driver comprises:
fourth and fifth n-channel transistors coupled between a drain of the first p-channel transistor and a drain of the second n-channel transistor, a gate of the fourth n-channel transistor coupled to receive the second bias voltage and a gate of the fifth n-channel transistor coupled to receive the first enable signal.

6. A receiver, comprising:
a pad splitter circuit coupled to a pad, the pad splitter circuit configured to generate a first logic signal and a second logic signal;
a wide-range receiver coupled to the pad splitter circuit to receive the first and second logic signals, the wide-range receiver comprising a combination of a first Schmitt trigger receiver and a second Schmitt trigger receiver and further comprising:
first, second, and third p-channel transistors coupled between a supply node and a top input node, a gate of the first p-channel transistor coupled to receive a first enable voltage, a gate of the second p-channel transistor coupled to receive a first bias voltage, and a gate of the third p-channel transistor coupled to receive the second logic signal;
a first n-channel transistor coupled between a bottom input node and a reference node, a gate of the first n-channel transistor coupled to receive the second logic signal; and
a first transmission gate coupled between the top input node and the bottom input node;

a control circuit coupled to the pad splitter circuit and the wide-range receiver; and
a bias generator circuit coupled to the pad splitter circuit and the wide-range receiver.

7. The receiver of claim 6 , wherein the wide-range receiver comprises:
fourth and fifth p-channel transistors coupled between the supply node and the top input node, a gate of the fourth p-channel transistor coupled to receive a second enable voltage, and a gate of the fifth p-channel transistor coupled to receive the first logic signal; and
sixth and seventh p-channel transistors, and second and third n-channel transistors(MNT 0 , MN 4 ), coupled between the top input node and the bottom input node, a gate of the sixth p-channel transistor coupled to receive the first bias voltage, a gate of the third n-channel transistor coupled to receive a second bias voltage.

8. The receiver of claim 7 , wherein the wide-range receiver comprises:
eighth and ninth p-channel transistors coupled between the supply node and the top input node; and
tenth and eleventh p-channel transistors coupled between the supply node and a top output node;
where a gate of the eighth p-channel transistor is coupled to a gate of the tenth p-channel transistor, a gate of the ninth p-channel transistor is coupled to the top output node, and a gate of the eleventh p-channel transistor is coupled to the top input node.

9. The receiver of claim 8 , wherein the wide-range receiver comprises:
twelfth and thirteenth p-channel transistors, and fourth and fifth n-channel transistors coupled between the top output node and a bottom output node, a gate of the twelfth p-channel transistor coupled to receive the first bias voltage, a gate of the fifth n-channel transistor coupled to receive the second bias voltage.

10. The receiver of claim 9 , wherein the wide-range receiver comprises:
a sixth n-channel transistor coupled between the bottom input node and the reference node;
a seventh n-channel transistor coupled between the bottom output node and the reference node;
wherein a gate of the sixth n-channel transistor is coupled to the bottom output node and a gate of the seventh n-channel transistor(MN 8 ) is coupled to the bottom input node.

11. The receiver of claim 10 , wherein the wide-range receiver comprises:
a second transmission gate coupled between the top output node and the bottom output node.

12. The receiver of claim 6 , wherein the wide-range receiver includes first circuitry that provides a first resistance and second circuitry that provides a second resistance, the first resistance in parallel to the second resistance, and third circuitry that provides a third resistance, coupled in series with the parallel combination of the first resistance, and wherein the combination of the first, second, and third resistance controls a trigger point of the wide-range receiver.

13. A transceiver, comprising:
a transmitter that includes:
an input circuit configured to couple a logic signal to a first node and a second node;
a first level-shifter having an input coupled to the first node;
a first pre-driver having an input coupled to an output of the first level-shifter;
a second-level shifter having an input coupled to the second node;
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Assignees

• Xilinx Inc

Inventors

• Ekambaram Sabarathnam
• Akurathi Vss Prasad Babu
• Goel Milind
• Dubey Hari Bilash

Classifications

• H03K19/018521 Primary

  of complementary type, e.g. CMOS · CPC title

• H04B1/44

  Transmit/receive switching · CPC title

• H04B1/0475

  with means for limiting noise, interference or distortion (H04B1/0483 takes precedence) · CPC title

• H04B1/005

  adapting radio receivers, transmitters andtransceivers for operation on two or more bands, i.e. frequency ranges · CPC title

• H04B1/586 Primary

  using an electronic circuit · CPC title