Configuration of a reconfigurable data processor using sub-files

Patent metadata

Field	Value
Publication number	US-11609769-B2
Application number	US-202017093543-A
Country	US
Kind code	B2
Filing date	Nov 9, 2020
Priority date	Nov 21, 2018
Publication date	Mar 21, 2023
Grant date	Mar 21, 2023

Abstract

A reconfigurable data processor comprises a bus system, and an array of configurable units connected to the bus system, configurable units in the array including configuration data stores to store unit files comprising a plurality of sub-files of configuration data particular to the corresponding configurable units. Configurable units in the plurality of configurable units each include logic to execute a unit configuration load process, including receiving via the bus system, sub-files of a unit file particular to the configurable unit, and loading the received sub-files into the configuration store of the configurable unit. A configuration load controller connected to the bus system, including logic to execute an array configuration load process, including distributing a configuration file comprising unit files for a plurality of the configurable units in the array.

First claim

What is claimed is:

1. A reconfigurable data processor, comprising:
a bus system;
an array of configurable units connected to the bus system, a configurable unit in the array including a configuration data store to store a unit file comprising a plurality of ordered sub-files of configuration data, the configuration data store comprising a configuration serial chain;
wherein the configurable unit includes logic to execute a unit configuration load process, including receiving,. via the bus system, a sub-file of the plurality of ordered sub-files, loading the received sub-file in parallel into the configuration data store, and serially shifting data of the received sub-file into the configuration serial chain; and
a configuration load controller connected to the bus system, including logic to execute an array configuration load process, including distributing a configuration file comprising unit files for the array of configurable units, the unit files each comprising a plurality of ordered sub-files.

2. The processor of claim 1 , wherein the plurality of ordered sub-files includes a first sub-file ordered before a second sub-file, both the first sub-file and the second sub-file particular to the configurable unit, and
the unit configuration load process comprises:
receiving the first sub-file from the bus system in a first bus cycle,
beginning to push the received first sub-file into the configuration serial chain during a second bus cycle after the first bus cycles,
receiving the second sub-file from the bus system in a third bus cycle after the second bus cycle, and
beginning to push the received second sub-file into the configuration serial chain during in a fourth bus cycle after the third bus cycle and occurring after the first sub-file has been fully pushed into the configuration serial chain.

3. The processor of claim 1 , wherein the array configuration load process includes receiving from a host process, a configuration load command identifying a location in memory of the configuration file, and generating one or more memory access requests in response to the command to retrieve the configuration file.

4. The processor of claim 1 , wherein the configuration file includes a plurality of sub-files, the plurality of sub-files including a sub-file for each configurable unit of a plurality of configurable units in the array of configurable units, the plurality of sub-files being arranged in the configuration file in an interleaved fashion based on a physical configuration of the plurality of configurable units, and wherein the array configuration load process includes routing the sub-files of the plurality of sub-files to respective configurable units in the plurality of configurable units based on locations of the sub-files in the configuration file.

5. The processor of claim 1 , wherein sub-file of the plurality of ordered sub-files has a number N of bits of data, and the bus system is configured to transfer N bits of data in one bus cycle.

6. The processor of claim 1 , wherein the array includes a first configurable unit of a first type and a second configurable unit of a second type, a first unit file for the first configurable unit has a first number of sub-files, and a second unit file for the second configurable unit has a second number of sub-files different than the first number.

7. The processor of claim 1 , wherein the unit files in the configuration file include first unit files for configurable units of a first type in the array of configurable unit and second unit files for configurable units of a second type in the array of configurable unit, the first unit files include Z1 sub-files, and the second unit files include Z2 sub-files, where Z1 is less than Z2, and the array configuration load process includes:
retrieving segments of the configuration file including sub-file (i) of the first unit files and the second unit files, for (i) going from 0 to Z1-1, and then retrieving segments of the configuration file including sub-file (i) of the second unit files, for (i) going from Z1 to Z2-1.

8. The processor of claim 1 , wherein configurable units in the array of configurable units include respective load complete status logic connected in a daisy chain starting and ending at the array configuration load logic.

9. The processor of claim 1 , wherein the bus system includes a top level network including an external data interface and an array interface, and an array level network connected to the array interface and to the configurable units in the array of configurable units.

10. The processor of claim 1 , wherein configurable units in the plurality of configurable units use routes in the bus system during execution after configuration also used in the configuration load process.

11. The processor of claim 2 , wherein the third bus cycle occurs after the first sub-file has been fully pushed into the configuration serial chain.

12. The processor of claim 5 , wherein the plurality of ordered sub-files includes a first sub-file ordered before a second sub-file, both the first sub-file and the second sub-file particular to the configurable unit, and
the unit configuration load process comprises:
receiving the first sub-file from the bus system in a first bus cycle,
pushing the received first sub-file into the configuration serial chain during N bus cycles following the first bus cycle,
receiving the second sub-file from the bus system in a second bus cycle occurring after the N bus cycles following the first bus cycle, and
pushing the received second sub-file into the configuration serial chain during N bus cycles following the second bus cycle.

13. The processor of claim 8 , wherein the array configuration load logic forwards a load complete signal on the daisy chain after the configuration file is distributed, and in each configurable unit in the array, the load complete status logic forwards the load complete signal on the daisy chain when the load complete signal from a previous member of the daisy chain is received and loading of its unit file is completed.

14. The processor of claim 12 , wherein the array includes more than N configurable units.

15. The processor of claim 9 , wherein the array configuration load process includes receiving from a host process, a configuration load command identifying a location in memory of the configuration file, and generating one or more memory access requests via the top level network in response to the command to retrieve the configuration file through the external data interface.

16. The processor of claim 15 , wherein the array configuration load process routes sub-files of the configuration data to configurable units via the array level network using addresses implied by location of the sub-files in the configuration file.

17. A computer-implemented method for operating a reconfigurable data processor comprising a bus system and an array of configurable units connected to the bus system, a configurable unit in the array including a configuration data store to store a unit file comprising a plurality of ordered sub-files of configuration data particular to the configurable unit, the configuration data store comprising a configuration serial chain, the method comprising:
distributing a configuration file comprising the unit file for the configurable unit, the unit files comprising a plurality of ordered sub-files, including a first sub-file and a second sub-file ordered after than the first sub-file; and
receiving in the configurable unit, the first sub-file, loading the received first sub-file in parallel into th

Assignees

• Sambanova Systems Inc

Inventors

• Shah Manish K
• Sivaramakrishnan Ram
• Luttrell Mark
• Jackson David B
• Prabhakar Raghu
• Jairath Sumti
• Grohoski Gregory Frederick
• Nataraja Pramod

Classifications

• G06F9/44505 Primary

  Configuring for program initiating, e.g. using registry, configuration files · CPC title

• G06F15/7867 Primary

  with reconfigurable architecture · CPC title

• G06F15/7871 Primary

  Reconfiguration support, e.g. configuration loading, configuration switching, or hardware OS · CPC title

• G06F13/4282

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title