Helical plated through-hole package inductor

US11608564B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11608564-B2
Application numberUS-202117213622-A
CountryUS
Kind codeB2
Filing dateMar 26, 2021
Priority dateDec 17, 2015
Publication dateMar 21, 2023
Grant dateMar 21, 2023

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Devices and methods including a though-hole inductor for an electronic package are shown herein. Examples of the through-hole inductor include a substrate including at least one substrate layer. Each substrate layer including a dielectric layer having a first surface and a second surface. An aperture included in the dielectric layer is located from the first surface to the second surface. The aperture includes an aperture wall from the first surface to the second surface. A conductive layer is deposited on the first surface, second surface, and the aperture wall. At least one coil is cut from the conductive layer and located on the aperture wall.

First claim

Opening claim text (preview).

The claimed invention is: 1. An electronic package including a through-hole inductor comprising: a substrate including a substrate layer, the substrate layer including a dielectric layer having a first surface and an opposing second surface; an aperture in the dielectric layer located from the first surface to the second surface, the aperture including an aperture wall extended from the first surface to the second surface; a conductive layer on the first surface and the second surface; a die coupled to the substrate and electrically coupled with the conductive layer; and an integrated voltage regulator (IVR) including: at least one coil including a first revolution and a second revolution, wherein the first revolution includes a top surface and the second revolution includes a bottom surface, wherein the top surface faces the bottom surface and the top surface is directly superjacent to the bottom surface, the at least one coil located on the aperture wall from the first surface to the second surface and coupled to the conductive layer on at least one of the first surface or second surface; and a magnetic core disposed in the aperture, wherein the magnetic core is disposed directly between the top surface of the first revolution and the bottom surface of the second revolution. 2. The package of claim 1 further comprising at least one capacitor or resistor located on the die. 3. The electronic package of claim 1 , wherein the magnetic core includes magnetic particles suspended within a carrier. 4. The electronic package of claim 3 , wherein the magnetic core includes flux, polymer, or epoxy material with magnetic particles suspended therein. 5. The electronic package of claim 4 , wherein the magnetic core includes magnetic nanoparticles. 6. The electronic package of claim 1 , wherein the substrate includes a second substrate layer, the second substrate layer can include a secondary conductive layer, the secondary conductive layer includes at least one electrical contact configured for electrical communication. 7. The electronic package of claim 6 , wherein the substrate includes a substrate core and at least one second substrate layer includes a sequential layer build-up. 8. The electronic package of claim 1 , wherein the IVR includes a buck converter circuit. 9. The electronic package of claim 1 , wherein the at least one coil includes a helical shape. 10. The electronic package of claim 1 , wherein the at least one coil is located within the substrate above or beneath the die. 11. The electronic package of claim 1 , wherein the magnetic core is disposed on the aperture wall at a location above and below the at least one coil along a longitudinal axis of the aperture. 12. The electronic package of claim 1 , wherein the at least one coil includes a helical structure with multiple revolutions. 13. A device comprising: a substrate including a first surface and a second surface; an aperture in the substrate, the substrate including an aperture wall extended from the first surface to the second surface; a conductive layer on the first surface and the second surface; at least one coil including a first revolution and a second revolution, wherein the first revolution includes a top surface and the second revolution includes a bottom surface, wherein the top surface faces the bottom surface and the top surface is directly superjacent to the bottom surface, the at least one coil located on the aperture wall from the first surface to the second surface; and a magnetic core disposed in the aperture, wherein the magnetic core is disposed directly between the top surface and the bottom.

Assignees

Inventors

Classifications

  • Manufacturing of magnetic cores by mechanical means (magnetic cores per se H01F27/24) · CPC title

  • with stacked layers · CPC title

  • with the coil helically wound around a magnetic core · CPC title

  • After-treatment of electroplated surfaces · CPC title

  • Details of via holes for interconnecting the layers · CPC title

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What does patent US11608564B2 cover?
Devices and methods including a though-hole inductor for an electronic package are shown herein. Examples of the through-hole inductor include a substrate including at least one substrate layer. Each substrate layer including a dielectric layer having a first surface and a second surface. An aperture included in the dielectric layer is located from the first surface to the second surface. The a…
Who is the assignee on this patent?
Intel Corp
What technology area does this patent fall under?
Primary CPC classification C25D7/00. Mapped technology areas include Chemistry & Metallurgy.
When was this patent published?
Publication date Tue Mar 21 2023 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).