Analog-to-digital converter with interpolation

Patent metadata

Field	Value
Publication number	US-11595053-B2
Application number	US-202117366506-A
Country	US
Kind code	B2
Filing date	Jul 2, 2021
Priority date	Dec 12, 2018
Publication date	Feb 28, 2023
Grant date	Feb 28, 2023

Abstract

An analog-to-digital converter (ADC) including: a signal input adapted to receive an analog signal; a first reference voltage input adapted to receive a first reference voltage; a second reference voltage input adapted to receive a second reference voltage, the second reference voltage is different than the first reference voltage; a first delay circuit having a first delay input coupled to the signal input, a second delay input coupled to the first reference voltage input, a first delay output and a second delay output; a second delay circuit having a third delay input coupled to the signal input, a fourth delay input coupled to the second reference voltage input; a third delay output and a fourth delay output; a first comparator having a first comparator input coupled to the first delay output, a second comparator input coupled to the second delay output and a first comparator output; and a second comparator having a third comparator input coupled to the third delay output, a fourth comparator input coupled to the fourth delay output and a second comparator output.

First claim

What is claimed as new and desired to be protected by Letters Patent of the United States is:

1. An analog-to-digital converter (ADC) comprising:
a signal input adapted to receive an analog signal;
a first reference voltage input adapted to receive a first reference voltage;
a second reference voltage input adapted to receive a second reference voltage, the second reference voltage is different than the first reference voltage;
a first delay circuit having a first delay input coupled to the signal input, a second delay input coupled to the first reference voltage input, a first delay output and a second delay output;
a second delay circuit having a third delay input coupled to the signal input, a fourth delay input coupled to the second reference voltage input; a third delay output and a fourth delay output;
a first comparator having a first comparator input coupled to the first delay output, a second comparator input coupled to the second delay output and a first comparator output; and
a second comparator having a third comparator input coupled to the third delay output, a fourth comparator input coupled to the fourth delay output and a second comparator output.

2. The ADC of claim 1 , further comprising:
a third comparator having a fifth comparator input coupled to the first comparator output, a sixth comparator input coupled to the second comparator output and a third comparator output.

3. The ADC of claim 2 , wherein the third comparator output is a single-bit digital representation of the analog signal.

4. The ADC of claim 1 , further comprising:
multiplexing logic circuitry having a first MUX input coupled to the first comparator output, a second MUX input coupled to the second comparator output, a first MUX output and a second MUX output.

5. The ADC of claim 4 , wherein the multiplexing logic circuitry further includes:
a first dummy comparator having a first dummy input coupled to the first MUX input, and a first dummy output;
a second dummy comparator having a second dummy input coupled to the second MUX input, and a second dummy output;
a first interpolation comparator having a first interpolation input coupled to the first MUX input, a second interpolation input coupled to the second MUX input, a first interpolation output and a second interpolation output;
a first logic gate having a first logic input coupled to the first dummy output, a second logic input coupled to the first interpolation output, and a first logic output;
a second logic gate having a third logic input coupled to the second interpolation output, a fourth logic input coupled to the second dummy output, and a second logic output;
a first switch element having a first switch input coupled to the first dummy output, a second switch input coupled to the first interpolation output, a third switch input coupled to the first logic output, a first switch output coupled to the first MUX output, and a second switch output coupled to the second MUX output; and
a second switch element having a fourth switch input coupled to the second interpolation output, a fifth switch input coupled to the second dummy output, a sixth switch input coupled to the second logic output, a third switch output coupled to the first MUX output, and a fourth switch output coupled to the second MUX output.

6. A multiplexing logic circuit comprising:
a first MUX input;
a second MUX input;
a first MUX output;
a second MUX output;
a first dummy comparator having a first dummy input coupled to the first MUX input, and a first dummy output;
a second dummy comparator having a second dummy input coupled to the second MUX input, and a second dummy output;
a first interpolation comparator having a first interpolation input coupled to the first MUX input, a second interpolation input coupled to the second MUX input, a first interpolation output and a second interpolation output;
a first logic gate having a first logic input coupled to the first dummy output, a second logic input coupled to the first interpolation output, and a first logic output;
a second logic gate having a third logic input coupled to the second interpolation output, a fourth logic input coupled to the second dummy output, and a second logic output;
a first switch element having a first switch input coupled to the first dummy output, a second switch input coupled to the first interpolation output, a third switch input coupled to the first logic output, a first switch output coupled to the first MUX output, and a second switch output coupled to the second MUX output; and
a second switch element having a fourth switch input coupled to the second interpolation output, a fifth switch input coupled to the second dummy output, a sixth switch input coupled to the second logic output, a third switch output coupled to the first MUX output, and a fourth switch output coupled to the second MUX output.

7. The multiplexing logic circuitry of claim 6 , wherein the first logic gate is an AND gate and the second logic gate is an AND gate.

8. An analog-to-digital converter (ADC) comprising:
a signal input adapted to receive an analog signal;
a plurality of delay circuits, each having a first delay input coupled to the signal input, a second delay input coupled to a reference voltage different than the reference voltage applied to other of the plurality of delay circuits, and a delay output;
a plurality of comparators, each having a comparator input coupled to the delay output of a corresponding one of the plurality of delay circuits, and a comparator output; and
a multiplexing logic circuit having a first MUX output, a second MUX output and a plurality of MUX inputs, each MUX input is coupled to the comparator output of one of the plurality of comparators.

9. The ADC of claim 8 , further comprising:
a first dummy comparator having a first dummy input coupled to the first MUX output, and a first dummy output;
a second dummy comparator having a second dummy input coupled to the second MUX output, and a second dummy output;
a first interpolation comparator having a first interpolation input coupled to the first MUX output, a second interpolation input coupled to the second MUX output, a first interpolation output and a second interpolation output.

Assignees

• Texas Instruments Inc

Inventors

• Soundararajan Rishi
• Pentakota Visvesvaraya

Classifications

• H03M1/204 Primary

  in which one or more virtual intermediate reference signals are generated between adjacent original reference signals, e.g. by connecting pre-amplifier outputs to multiple comparators · CPC title

• H03M1/207 Primary

  using a digital interpolation circuit · CPC title

• H03M1/206

  using a logic interpolation circuit · CPC title