Cache device and semiconductor device including a tag memory storing absence, compression and write state information

Patent metadata

Field	Value
Publication number	US-10019375-B2
Application number	US-201615269930-A
Country	US
Kind code	B2
Filing date	Sep 19, 2016
Priority date	Mar 2, 2016
Publication date	Jul 10, 2018
Grant date	Jul 10, 2018

Abstract

A cache device has a data memory capable of storing a piece of first cache line data and a piece of second cache line data for first and second ways in compressed form, and a tag memory configured to store, for each of the pieces of cache line data, a piece of tag data including uncompressed data writing state information, an absence flag, and a compression information field. In case of modifying only part of a cache line, i.e., a partial write, a request converter converts a write request into a read request, and a read-out piece of data is decompressed and written in a write status buffer. Data may be written from the write status buffer to the data memory without being compressed, which eliminates a need for decompression and compression for every writing or modifying operation of a piece of partial data, thereby reducing latency and power consumption.

First claim

What is claimed is:

1. A cache device comprising:
a data memory configured to store a piece of first cache line data and a piece of second cache line data for first and second ways in compressed form;
a tag memory configured to store, for each of the pieces of cache line data, a piece of tag data including a piece of uncompressed data writing state information, a piece of absence information, and a piece of compression information;
a first decompressor; and
a judgment section configured to judge, upon receipt of a write request from a master device connected to the cache device, whether a piece of data to be written associated with the write request is present in the piece of first cache line data,
wherein if the judgment section judges that the piece of data to be written is present in the piece of first cache line data, the piece of first cache line data is decompressed by the first decompressor, the piece of data to be written is written on the decompressed piece of data, and the piece of data to be written after the writing on the decompressed piece of data is compressed and stored in the data memory.

2. The cache device according to claim 1 , wherein if available space enough to store the decompressed piece of data is absent in a storage region for the piece of first cache line data, the decompressed piece of data is written across the storage region for the piece of first cache line data and a storage region for the piece of second cache line data after the piece of second cache line data is saved in another memory.

3. The cache device according to claim 2 , wherein when the piece of second cache line data is saved in the other memory, the piece of absence information for the piece of second cache line data is modified to a value indicating that the piece of second cache line data is not present in the data memory.

4. The cache device according to claim 3 , further comprising:
a compressor,
wherein when writing of the piece of data to be written on the piece of first cache line data is performed a predetermined number of times, the compressor compresses the decompressed piece of data and writes the compressed piece of data in the storage region for the piece of first cache line data.

5. The cache device according to claim 4 , wherein when the compressor writes the compressed piece of first cache line data in the storage region for the piece of first cache line data, the piece of second cache line data saved in the other memory is written back to the storage region for the piece of second cache line data, and the piece of absence information for the piece of second cache line data is modified to a value indicating that the piece of second cache line data is present in the data memory.

6. The cache device according to claim 2 , further comprising:
a coherence control section configured to, upon receipt of a read request for the piece of second cache line data saved in the other memory, obtain the piece of second cache line data from the other memory, decompress the piece of second cache line data obtained from the other memory, and transmit the decompressed piece of second cache line data to a request source of the read request.

7. The cache device according to claim 6 , further comprising:
a second decompressor configured to decompress the piece of second cache line data.

8. The cache device according to claim 6 , wherein the decompression of the piece of second cache line data is performed by the first decompressor.

9. The cache device according to claim 1 , wherein the piece of uncompressed data writing state information comprises a dirty bit indicating whether or not a corresponding piece of cache line data has been modified.

10. A semiconductor device comprising:
a central processing unit (CPU); and
a cache device,
wherein the cache device comprises:
a data memory configured to store a piece of first cache line data and a piece of second cache line data for first and second ways in compressed form; and
a tag memory configured to store, for each of the pieces of cache line data, a piece of tag data including a piece of uncompressed data writing state information, a piece of absence information, and a piece of compression information,

wherein the semiconductor device further comprises:
an interconnect connected to the cache device;
a first decompressor provided in the cache device; and
a judgment section provided in the cache device and configured to judge, upon receipt of a write request from the CPU, whether a piece of data to be written associated with the write request is present in the piece of first cache line data, and

wherein if the judgment section judges that the piece of data to be written is present in the piece of first cache line data, the piece of first cache line data is decompressed by the first decompressor, the piece of data to be written is written on the decompressed piece of data, and the piece of data to be written after the writing on the decompressed piece of data is compressed and stored in the data memory.

11. The semiconductor device according to claim 10 , wherein if available space enough to store the decompressed piece of data is absent in a storage region for the piece of first cache line data, the cache device writes the decompressed piece of data across the storage region for the piece of first cache line data and a storage region for the piece of second cache line data after the cache device saves the piece of second cache line data in another memory via the interconnect.

12. The semiconductor device according to claim 11 , wherein when the piece of second cache line data is saved in the other memory, the piece of absence information for the piece of second cache line data is modified to a value indicating that the piece of second cache line data is not present in the data memory.

13. The semiconductor device according to claim 12 , further comprising:
a compressor provided in the cache device,
wherein when writing of the piece of data to be written on the piece of first cache line data is performed a predetermined number of times, the compressor compresses the decompressed piece of data and writes the compressed piece of data in the storage region for the piece of first cache line data.

14. The semiconductor device according to claim 13 , wherein when the compressor writes the compressed piece of first cache line data in the storage region for the piece of first cache line data, the piece of second cache line data saved in the other memory is written back to the storage region for the piece of second cache line data, and the piece of absence information for the piece of second cache line data is modified to a value indicating that the piece of second cache line data is present in the data memory.

15. The semiconductor device according to claim 11 , further comprising:
a coherence control section provided in the cache device and configured to, upon receipt of a read request for the piece of second cache line data saved in the other memory, obtain the piece of second cache line data from the other memory, decompress the piece of second cache line data acquired obtained from the other memory, and transmit the decompressed piece of second cache line data to a request source of the read request.

16. The semiconductor device according to claim 15 , further comprising:
a second decompressor provided in the cache device and configured to decompress the piece of second cache line data.

17. The semiconductor device according to claim 15 , wherein the decompression of the piece of second cache line data is performed by

Assignees

• Toshiba Memory Corp

Inventors

• Usui Hiroyuki
• Maeda Seiji

Classifications

• G06F12/0811

  with multilevel cache hierarchies · CPC title

• G06F2212/1028

  Power efficiency · CPC title

• G06F2212/6042

  Allocation of cache space to multiple users or processors · CPC title

• G06F12/084

  with a shared cache · CPC title

• G06F12/0864

  using pseudo-associative means, e.g. set-associative or hashing · CPC title