Method for managing multi-channel memory device to have improved channel switch response time and related memory control system

Patent metadata

Field	Value
Publication number	US-10037275-B2
Application number	US-201514930665-A
Country	US
Kind code	B2
Filing date	Nov 3, 2015
Priority date	Aug 15, 2014
Publication date	Jul 31, 2018
Grant date	Jul 31, 2018

Abstract

A method for managing a multi-channel memory device includes at least following steps: when the multi-channel memory device is controlled to operate in an M-channel mode, reserving a partial memory space in the multi-channel memory device that is not used under the M-channel mode, where M and N are positive integers, and M is smaller than N; and when the multi-channel memory device is controlled to switch from the M-channel mode to an N-channel mode, accessing data in the reserved partial memory space used under the N-channel mode.

First claim

What is claimed is:

1. A method for managing a multi-channel memory device comprising:
when the multi-channel memory device is controlled to switch from an M-channel mode to an N-channel mode, accessing data of at least one first memory region in a partial memory space at M memory channels used under the M-channel mode before accessing data of at least one second memory region in the partial memory space at the M memory channels used under the M-channel mode;
wherein M and N are positive integers and M is smaller than N; and a bandwidth requirement associated with all data of the at least one first memory region is higher than a bandwidth requirement associated with all data of the at least one second memory region.

2. The method of claim 1 , wherein the M memory channels are included in N memory channels used under the N-channel mode.

3. The method of claim 1 , further comprising:
recording a memory address of the at least one first memory region under the M-channel mode;
wherein accessing data of the at least one first memory region in the partial memory space at the M memory channels used under the M-channel mode comprises:
referring to the recorded memory address of the at least one first memory region for performing data access upon the at least one first memory region in the partial memory space at the M memory channels.

4. The method of claim 1 , further comprising:
when or before the multi-channel memory device is controlled to operate in the M-channel mode, sorting stored data of memory regions in a memory space according to a bandwidth requirement order;
wherein accessing data of the at least one first memory region in the partial memory space at the M memory channels used under the M-channel mode comprises:
performing data access upon memory regions in the partial memory space at the M memory channels according to a predetermined memory address order of the memory regions.

5. A memory control system for managing a multi-channel memory device comprising:
a mode controlling module, arranged to control the multi-channel memory device to switch from an M-channel mode to an N-channel mode, wherein M and N are positive integers, and M is smaller than N; and
a memory access controlling circuit, wherein when the multi-channel memory device is controlled to switch from the M-channel mode to the N-channel mode, the memory access controlling circuit is arranged to access data of at least one first memory region in a partial memory space at M memory channels used under the M-channel mode before accessing data of at least one second memory region in the partial memory space at the M memory channels used under the M-channel mode, where a bandwidth requirement associated with all data of the at least one first memory region is higher than a bandwidth requirement associated with all data of the at least one second memory region.

6. The memory control system of claim 5 , wherein the M memory channels are included in N memory channels used under the N-channel mode.

7. The memory control system of claim 5 , wherein the memory access controlling circuit is further arranged to record a memory address of the at least one first memory region under the M-channel mode; and the memory access controlling circuit refers to the recorded memory address of the at least one first memory region for performing data access upon the at least one first memory region in the partial memory space at the M memory channels.

8. The memory control system of claim 5 , wherein when or before the multi-channel memory device is controlled to operate in the M-channel mode, the memory access controlling circuit is further arranged to sort stored data of memory regions in a memory space according to a bandwidth requirement order, where the memory access controlling circuit performs data access upon memory regions in the partial memory space at the M memory channels according to a predetermined memory address order of the memory regions.

Assignees

• Mediatek Inc

Inventors

• Liu Chuan
• Kuo Wen-Hsuen

Classifications

• G06F2212/1016

  Performance improvement · CPC title

• G06F13/16

  for access to memory bus (G06F13/28 takes precedence) · CPC title

• G06F2212/251

  Local memory within processor subsystem · CPC title

• G06F12/06

  Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication (G06F12/08 takes precedence) · CPC title

• G06F13/1694 Primary

  Configuration of memory controller to different memory types · CPC title