Efficient and selective sparing of bits in memory systems
US-11698842-B2 · Jul 11, 2023 · US
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Glancy Stephen patents
Glancy Stephen is listed as an inventor on 16 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Glancy Stephen |
| Total patents | 16 |
| First publication | Jun 6, 2019 |
| Latest publication | Jul 11, 2023 |
Notable patents
Publications ranked by popularity score, then publication date.
Method and apparatus to reduce bandwidth overhead of CRC protection on a memory channel
US-11593196-B2 · Feb 28, 2023 · US
Method and apparatus to reduce bandwidth overhead of crc protection on a memory channel
US-2022091927-A1 · Mar 24, 2022 · US
Efficient and selective sparing of bits in memory systems
US-2022027243-A1 · Jan 27, 2022 · US
Method and apparatus to reduce bandwidth overhead of CRC protection on a memory channel
US-11200112-B1 · Dec 14, 2021 · US
Efficient and selective sparing of bits in memory systems
US-11182262-B2 · Nov 23, 2021 · US
Self-correcting temperature and notification system
US-2021267453-A1 · Sep 2, 2021 · US
Hardware abstraction in software or firmware for hardware calibration
US-10936222-B2 · Mar 2, 2021 · US
Hardware abstraction in software or firmware for hardware calibration
US-2020401330-A1 · Dec 24, 2020 · US
Efficient and selective sparing of bits in memory systems
US-2020226040-A1 · Jul 16, 2020 · US
Recent patents
Latest publications not already listed above.
Efficient and selective sparing of bits in memory systems
US-10671497-B2 · Jun 2, 2020 · US
Internally-generated data storage in spare memory locations
US-10606696-B2 · Mar 31, 2020 · US
Simulating a single data rate (SDR) mode on a dual data rate (DDR) memory controller for calibrating DDR memory coarse alignment
US-10580476-B2 · Mar 3, 2020 · US
Efficient and Selective Sparing of Bits in Memory Systems
US-2019227886-A1 · Jul 25, 2019 · US
Simulating a single data rate (sdr) mode on a dual data rate (ddr) memory controller for calibrating ddr memory coarse alignment
US-2019214073-A1 · Jul 11, 2019 · US
Internally-generated data storage in spare memory locations
US-2019171520-A1 · Jun 6, 2019 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| IBM | 16 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G06F11/1048 | 11 |
| G06F11/1068 | 11 |
| G11C29/52 | 8 |
| G06F11/1666 | 6 |
| G11C2029/1204 | 6 |