Semiconductor memory device, electronic system including the same, and method for fabricating the same

Patent metadata

Field	Value
Publication number	US-11574883-B2
Application number	US-202117389841-A
Country	US
Kind code	B2
Filing date	Jul 30, 2021
Priority date	Oct 22, 2020
Publication date	Feb 7, 2023
Grant date	Feb 7, 2023

Abstract

A semiconductor memory device includes a first substrate including opposite first and second surfaces, a mold structure including gate electrodes stacked on the first surface of the first substrate, a channel structure through the mold structure, a first contact via penetrating the first substrate, a second substrate including opposite third and fourth surfaces, a circuit element on the third surface of the second substrate, a first through-via through the mold structure connecting the first contact via and the circuit element, the first through-via including a first conductive pattern, and a first spacer separating the first conductive pattern from the mold structure, and a second through-via through the mold structure and spaced apart from the first through-via, the second through-via including a second conductive pattern, and a second spacer separating the second conductive pattern from the first substrate and the mold structure.

First claim

What is claimed is:

1. A semiconductor memory device, comprising:
a first substrate including a first surface and a second surface opposite to each other;
a mold structure including a plurality of gate electrodes stacked sequentially on the first surface of the first substrate;
a channel structure which penetrates the mold structure and intersects the plurality of gate electrodes;
a first contact via penetrating the first substrate;
a second substrate including a third surface facing the first surface, and a fourth surface opposite to the third surface;
a circuit element on the third surface of the second substrate;
a first through-via through the mold structure, the first through-via connecting the first contact via and the circuit element, and the first through-via including:
a first conductive pattern, and
a first spacer film separating the first conductive pattern from the mold structure; and

a second through-via through the mold structure, the second through-via being spaced apart from the first through-via, and the second through-via including:
a second conductive pattern, and
a second spacer film separating the second conductive pattern from the first substrate and the mold structure.

2. The semiconductor memory device as claimed in claim 1 , wherein each of a width of the first through-via and a width of the second through-via decreases toward the first substrate.

3. The semiconductor memory device as claimed in claim 1 , wherein a width of the first contact via decreases toward the mold structure.

4. The semiconductor memory device as claimed in claim 1 , wherein the mold structure includes a through-via trench which exposes the first substrate, the second spacer film extending along a side surface and a lower surface of the through-via trench.

5. The semiconductor memory device as claimed in claim 1 , wherein the second conductive pattern does not connect the first contact via and the circuit element.

6. The semiconductor memory device as claimed in claim 1 , wherein the first contact via includes:
a third conductive pattern; and
a third spacer film which separates the third conductive pattern from the first substrate.

7. The semiconductor memory device as claimed in claim 1 , wherein the first substrate includes a substrate trench extending from the first surface, the first through-via and the second through-via being in the substrate trench.

8. The semiconductor memory device as claimed in claim 1 , further comprising a first input-output pad connected to the first contact via, the first input-output pad being on the second surface of the first substrate.

9. The semiconductor memory device as claimed in claim 8 , further comprising:
a second contact via penetrating the second substrate; and
a second input-output pad connected to the second contact via, the second input-output pad being on the fourth surface of the second substrate.

10. The semiconductor memory device as claimed in claim 1 , wherein each of the first through-via and the second through-via penetrates a first portion of the plurality of gate electrodes, and does not penetrate a second portion of the plurality of gate electrodes.

11. The semiconductor memory device as claimed in claim 1 , further comprising:
an interlayer insulating film covering the mold structure on the first substrate;
a third through-via spaced part from the mold structure, the third through-via penetrating the interlayer insulating film; and
a second input-output pad connected to the third through-via.

12. A semiconductor memory device, comprising:
a first substrate including a first surface and a second surface opposite to each other;
a mold structure including a plurality of gate electrodes stacked sequentially on the first surface of the first substrate;
a channel structure which penetrates the mold structure and intersects the plurality of gate electrodes;
a first through-via including:
a first conductive pattern through the mold structure, and
a first spacer film separating the first conductive pattern from the mold structure;

a second through-via including:
a second conductive pattern through the mold structure, and
a second spacer film separating the second conductive pattern from the first substrate and the mold structure;

an upper insulating film on the second surface of the first substrate;
a contact trench through the upper insulating film and the first substrate, the contact trench exposing the first conductive pattern;
a contact via including:
a third spacer film along side surfaces of the contact trench, and
a third conductive pattern connected to the first conductive pattern on the third spacer film;

an input-output pad connected to the contact via, the input-output pad being on the upper insulating film;
a second substrate includes a third surface facing the first surface, and a fourth surface opposite to the third surface; and
a first circuit element connected to the first through-via, the first circuit element being on the third surface of the second substrate.

13. The semiconductor memory device as claimed in claim 12 , wherein the channel structure includes:
a semiconductor pattern intersecting the plurality of gate electrodes; and
an information storage film between the semiconductor pattern and the mold structure.

14. The semiconductor memory device as claimed in claim 12 , further comprising:
a block separation region extending in a first direction to cut the mold structure; and
a bit line extending in a second direction intersecting the first direction, the bit line being connected to the channel structure between the mold structure and the second substrate.

15. The semiconductor memory device as claimed in claim 14 , further comprising:
a second circuit element connected to the bit line, the second circuit element being on the third surface of the second substrate; and
a third circuit element connected to each of the gate electrodes, the third circuit element being on the third surface of the second substrate.

16. An electronic system, comprising:
a main board;
a semiconductor memory device on the main board; and
a controller electrically connected to the semiconductor memory device, the controller being on the main board,
wherein the semiconductor memory device includes:
a first substrate having a first surface opposite a second surface,
a mold structure including a plurality of gate electrodes stacked sequentially on the first surface of the first substrate,
a channel structure which penetrates the mold structure and intersects the plurality of gate electrodes,
a contact via penetrating the first substrate, the contact via being electrically connected to the controller,
a second substrate including a third surface facing the first surface, and a fourth surface opposite to the third surface,
a circuit element on the third surface of the second substrate,
a first through-via through the mold structure, the first through-via connecting the contact via and the circuit element, and the first through-via including:
a first conductive pattern, and
a first spacer film separating the first conductive pattern from the mold structure; and

a second through-via through the mold structure, the second through-via being spaced apart from the first through-via, and the second through-via including:
a second conductive pattern, and
a second spacer film separating the second conductive pattern from the first substrate and the mold structure.

17. The electronic system as claimed in claim 16 , wherein the semiconductor memor

Assignees

• Samsung Electronics Co Ltd

Inventors

• Ahn Jae Ho
• Kim Ji Won
• Hwang Sung-Min
• Lim Joon-Sung
• Sung Suk Kang

Classifications

• H10W80/00

  Direct bonding of chips, wafers or substrates · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/24

  at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape · CPC title

• H10W72/823

  Interconnections through encapsulations, e.g. pillars through molded resin on a lateral side a chip · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title