Semiconductor device and manufacturing method of semiconductor device

Patent metadata

Field	Value
Publication number	US-2020286990-A1
Application number	US-201916510488-A
Country	US
Kind code	A1
Filing date	Jul 12, 2019
Priority date	Mar 7, 2019
Publication date	Sep 10, 2020
Grant date	—

Abstract

A semiconductor device including a first chip and a second chip. The first chip includes: a first substrate; a first transistor that is provided on the first substrate; and a first pad that is provided above the first transistor and that is electrically connected to the first transistor. The second chip includes: a second pad that is provided on the first pad; a second substrate that is provided above the second pad and that includes a first diffusion layer and a second diffusion layer, at least one of the first diffusion layer and the second diffusion layer being electrically connected to the second pad; and an isolation insulating film or an isolation trench that extends at least from an upper surface of the second substrate to a lower surface of the second substrate within the second substrate and that isolates the first diffusion layer from the second diffusion layer.

First claim

What is claimed is:

1 . A semiconductor device comprising:
a first chip including:
a first substrate;
a first transistor that is provided on the first substrate; and
a first pad that is provided above the first transistor and that is electrically connected to the first transistor; and
a second chip including:
a second pad that is provided on the first pad;
a second substrate that is provided above the second pad and that includes a first diffusion layer and a second diffusion layer, at least one of the first diffusion layer and the second diffusion layer being electrically connected to the second pad; and
an isolation insulating film or an isolation trench that extends at least from an upper surface of the second substrate to a lower surface of the second substrate within the second substrate and that isolates the first diffusion layer from the second diffusion layer.

2 . The semiconductor device according to claim 1 , wherein
the isolation insulating film or the isolation trench surrounds at least a portion of the second substrate.

3 . The semiconductor device according to claim 1 , wherein
the second chip further includes: a plug that extends from the upper surface of the second substrate to the lower surface of the second substrate within the second substrate, and a third pad that is provided on the plug.

4 . The semiconductor device according to claim 3 , wherein
the second chip includes the isolation insulating film, and the plug is provided within the second substrate and is surrounded by a first insulating film including a same material as a material of the isolation insulating film.

5 . The semiconductor device according to claim 4 , wherein the first insulating film and the isolation insulating film constitute a monolithic structure.

6 . The semiconductor device according to claim 4 , wherein
the plug is electrically connected to an interconnect layer within the first chip via the first and second pads.

7 . The semiconductor device according to claim 1 , wherein
the isolation insulating film or the isolation trench is provided between the first diffusion layer and the second diffusion layer.

8 . The semiconductor device according to claim 7 , wherein
the first diffusion layer and the second diffusion layer extend from the upper surface of the second substrate to the lower surface of the second substrate within the second substrate.

9 . The semiconductor device according to claim 8 , wherein
the isolation insulating film or the isolation trench surrounds at least one of the first and second diffusion layers.

10 . The semiconductor device according to claim 1 , wherein
the second chip further includes an insulating film that is provided on the second substrate, and the isolation insulating film or the isolation trench extends from an upper surface of the insulating film provided on the second substrate to the lower surface of the second substrate within the second substrate and the second insulating film provided on the second substrate.

11 . The semiconductor device according to claim 10 , wherein
the second chip comprises the isolation insulating film, and at least a portion of an upper surface of the isolation insulating film is provided at a position lower than a position of the upper surface of the second insulating film.

12 . A manufacturing method of a semiconductor device, comprising:
forming a first transistor on a first wafer; forming a first pad that is electrically connected to the first transistor of the first wafer above the first transistor; forming a first diffusion layer and a second diffusion layer within a second wafer; forming an isolation insulating film or an isolation trench that extends at least from an upper surface of the second wafer to a lower surface of the second wafer within the second wafer and that isolates the first diffusion layer from the second diffusion layer; forming a second pad that is electrically connected to at least one of the first diffusion layer and the second diffusion layer above the second wafer; bonding the first wafer and the second wafer so that the second pad is disposed on the first pad; and forming a chip by dicing the bonded wafers.

13 . The manufacturing method of the semiconductor device according to claim 12 , comprising
bonding the first wafer and the second wafer after forming the isolation insulating film or the isolation trench within the second wafer.

14 . The manufacturing method of the semiconductor device according to claim 12 , comprising
forming the isolation insulating film or the isolation trench within the second wafer after bonding the first wafer and the second wafer.

15 . The manufacturing method of the semiconductor device according to claim 12 , comprising:
forming the isolation insulating film that extends at least from the upper surface of the second wafer to the lower surface of the second wafer within the second wafer, wherein forming the isolation insulating film comprises polishing an upper surface of the substrate of the second wafer to expose an upper surface of the isolation insulating film from the substrate.

16 . The manufacturing method of the semiconductor device according to claim 15 , wherein polishing the substrate is performed such that the upper surface of the isolation insulating film is coplanar with the upper surface of the substrate of the second wafer.

17 . A semiconductor device comprising:
a first chip including:
a first pad; and
a first substrate that includes a first diffusion layer and a second diffusion layer, at least one of the first and second diffusion layers being electrically connected to the first pad; and
a first isolation insulating film disposed between a portion of the first diffusion layer and a portion of the second diffusion layer; and
a second chip including:
a second pad that is provided on and electrically connected to the first pad;
a second substrate that is provided above the second pad and that includes a third diffusion layer and a fourth diffusion layer, at least one of the third diffusion layer and fourth diffusion layer being electrically connected to the second pad; and
a second isolation insulating film that extends at least from an upper surface of the second substrate to a lower surface of the second substrate within the second substrate and that isolates the third diffusion layer from the fourth diffusion layer.

18 . The semiconductor device according to claim 17 , wherein:
the first substrate has an upper surface and a lower surface, and the first isolation insulating film extends from the upper surface of the first substrate to a position between the upper surface and the lower surface.

19 . The semiconductor device according to claim 18 , wherein an upper surface of the second isolation insulating film and the upper surface of the second substrate are coplanar.

20 . The semiconductor device according to claim 17 , wherein the first diffusion layer and the second diffusion layer are in contact.

Assignees

• Toshiba Memory Corp

Inventors

• Uchiyama Yasuhiro
• Arai Shinya
• Sakata Koichi
• Tomimatsu Takahiro

Classifications

• H10W20/0234

  comprising etching via holes that stop on pads or on electrodes · CPC title

• H10W20/0242

  comprising etching via holes from the back sides of the chips, wafers or substrates · CPC title

• H10W20/0253

  comprising forming the through-semiconductor vias after stacking of the chips, wafers or substrates · CPC title

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10W10/061

  using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations · CPC title