Semiconductor memory device

Patent metadata

Field	Value
Publication number	US-2022270992-A1
Application number	US-202117304057-A
Country	US
Kind code	A1
Filing date	Jun 14, 2021
Priority date	Feb 24, 2021
Publication date	Aug 25, 2022
Grant date	—

Abstract

A semiconductor memory device includes: a stack above a peripheral circuit on a first substrate, in which first conductive layers and first insulation layers are alternately stacked in a first direction each; a first pillar through the stack, in which a semiconductor layer and each first conductive layer form a memory cell at their intersection; a second substrate including a first region above the stack and the first pillar, being connected to a semiconductor layer, and a second region juxtaposed with the first region in a second direction; a second insulation layer through the second substrate, insulating the regions from each other; and a second conductive layer including a first portion through the second substrate, and a second portion extending in the second direction above the second substrate and including a part defining a bonding pad. The second portion overlaps with the second insulation layer in the first direction.

First claim

What is claimed is:

1 . A semiconductor memory device, comprising:
a first substrate; a peripheral circuit provided on the first substrate; a stack provided above the peripheral circuit and including first conductive layers and first insulation layers, each first conductive layer and each first insulation layer being alternately stacked in a first direction; a first pillar penetrating through the stack in the first direction and including a semiconductor layer, the semiconductor layer and the each first conductive layer forming a memory cell at an intersection therebetween; a second substrate including a first region and a second region, the first region being provided above the stack and the first pillar and being electrically connected to the semiconductor layer, and the second region being juxtaposed with the first region in a second direction intersecting with the first direction; a second insulation layer penetrating through the second substrate in the first direction, extending in a third direction intersecting with the first direction and with the second direction, and electrically insulating the first and second regions from each other; and a second conductive layer including a first portion and a second portion, the first portion penetrating through the second substrate in the first direction, the second portion extending in the second direction above the second substrate, and the second portion including a part defining a bonding pad, the second portion overlapping with the second insulation layer in the first direction.

2 . The device according to claim 1 , wherein:
the stack includes a step portion provided at an end portion of the stack in the second direction, the each first conductive layer and the each second conductive layer being stacked in tiers; and the semiconductor memory device further comprises a second pillar, the second pillar penetrating through the stack in the first direction, being provided between the first pillar and the step portion, and being electrically insulated from the peripheral circuit.

3 . The device according to claim 2 , wherein
the second insulation layer does not overlap with the stack in the first direction.

4 . The device according to claim 2 , wherein
the second insulation layer overlaps with the step portion in the first direction.

5 . The device according to claim 2 , further comprising
a plug extending in the first direction and electrically connecting the first portion and the peripheral circuit, wherein the first portion overlaps with the step portion in the first direction.

6 . A semiconductor memory device, comprising:
a first substrate; a peripheral circuit provided on the first substrate; a stack provided above the peripheral circuit and including first conductive layers and first insulation layers, each first conductive layer and each first insulation layer being alternately stacked in a first direction; a first pillar penetrating through the stack in the first direction and including a semiconductor layer, the semiconductor layer and the each first conductive layer forming a memory cell at an intersection therebetween; a second substrate including a first region and a second region, the first region being provided above the stack and the first pillar and being electrically connected to the semiconductor layer, and the second region being juxtaposed the first region in a second direction intersecting with the first direction; a second insulation layer penetrating through the second substrate in the first direction, extending in a third direction intersecting with the first direction and the second direction, and electrically insulating the first region from the second region; and a second conductive layer including a first portion and a second portion, the first portion penetrating through the second substrate in the first direction, the second portion extending in the second direction above the second substrate, and the second portion including a part defining a bonding pad, the first portion being provided between the first region and the second insulation layer.

7 . The device according to claim 6 , wherein:
the stack includes a step portion provided at an end portion of the stack in the second direction, the each first conductive layer and the each second conductive layer being arranged in tiers; and the semiconductor memory device further comprises a second pillar, the second pillar penetrating through the stack in the first direction, being provided between the first pillar and the step portion, and being electrically insulated from the peripheral circuit.

8 . The device according to claim 7 , further comprising
a plug extending in the first direction and electrically connecting the first portion and the peripheral circuit, wherein: the first portion overlaps with the step portion in the first direction; and the second insulation layer does not overlap with the step portion in the first direction.

9 . The device according to claim 7 , further comprising
a plug extending in the first direction and electrically connecting the first portion and the peripheral circuit, wherein: the plug is provided between the first pillar and the step portion; and the second insulation layer overlaps with the step portion in the first direction.

10 . The device according to claim 7 , further comprising
a plug extending in the first direction and electrically connecting the first portion and the peripheral circuit, wherein: the plug is provided between the first pillar and the step portion; and the second insulation layer overlaps with the stack in the first direction but does not overlap with the step portion.

11 . The device according to claim 7 , further comprising
a plug extending in the first direction and electrically connecting the first portion and the peripheral circuit, wherein: the plug is provided between the first pillar and the step portion; and the second portion overlaps with the second region in the first direction.

Assignees

• Kioxia Corp

Inventors

• Wada Hideo

Classifications

• H10W90/792

  between multiple chips · CPC title

• H10W80/327

  characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers · CPC title

• H10W80/312

  characterised by the direct bonding of electrically conductive pads · CPC title

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W80/00

  Direct bonding of chips, wafers or substrates · CPC title