Semiconductor device and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-2022068858-A1
Application number	US-202117189696-A
Country	US
Kind code	A1
Filing date	Mar 2, 2021
Priority date	Aug 31, 2020
Publication date	Mar 3, 2022
Grant date	—

Abstract

A semiconductor device includes a first substrate, a first insulating film provided on the first substrate, and a first plug provided in the first insulating film. The device further includes a first layer provided on the first insulating film and a first metal layer provided on the first plug in the first layer and electrically connected to the first plug. The device further includes a second metal layer including a first portion provided in the first layer and a second portion provided on the first layer and electrically connected to the first metal layer.

First claim

What is claimed is:

1 . A semiconductor device comprising:
a first substrate; a first insulating film disposed on the first substrate; a first plug disposed in the first insulating film; a first layer disposed on the first insulating film; a first metal layer disposed on and electrically connected to the first plug; and a second metal layer including (i) a first portion provided in the first layer and (ii) a second portion disposed on the first layer and electrically connected to the first metal layer.

2 . The semiconductor device according to claim 1 , wherein the first layer includes a second substrate.

3 . The semiconductor device according to claim 2 , wherein the first layer further includes a second insulating film disposed on an upper surface and a side surface of the second substrate.

4 . The semiconductor device according to claim 3 , wherein
the first plug contains a first metal element, and the first metal layer contains a second metal element different from the first metal element.

5 . The semiconductor device according to claim 4 , wherein
the first metal element includes a tungsten (W) element, and the second metal element includes at least one of an aluminum (Al) element, a hafnium (Hf) element, or a zirconium (Zr) element.

6 . The semiconductor device according to claim 1 , wherein:
the first plug includes N plugs, N being an integer of at least 2; and the first metal layer includes N metal layers provided on the N plugs.

7 . The semiconductor device according to claim 1 , wherein:
the first plug includes N plugs, N being an integer of least 2; and the first metal layer includes one metal layer disposed on the N plugs.

8 . The semiconductor device according to claim 1 , wherein the second portion of the second metal layer includes a bonding pad.

9 . A semiconductor device comprising:
a first insulating film; a first plug disposed in the first insulating film; a substrate disposed on the first insulating film; a first metal layer disposed on and electrically connected to the first plug; and a second metal layer including (i) a first portion provided in the substrate and (ii) a second portion disposed on the substrate and electrically connected to the first metal layer.

10 . The semiconductor device according to claim 9 , further comprising a second insulating film provided on an upper surface and a side surface of the substrate, wherein
the first portion is disposed in the substrate and the second insulating film, and the second portion is disposed on the substrate and the second insulating film.

11 . A method of manufacturing a semiconductor device comprising:
providing a first substrate and a second substrate; forming a first metal layer in the second substrate; forming a first plug on the first metal layer; adhering the first substrate to the second substrate via the first plug and the first metal layer; forming a first opening in the second substrate to expose the first metal layer; and forming a second metal layer in the first opening, the second metal layer being electrically connected to the first plug.

12 . The method according to claim 11 , wherein the forming the first opening includes using a gas containing a fluorine (F) element.

13 . The method according to claim 11 , wherein
the first plug contains a first metal element, and the first metal layer contains a second metal element different from the first metal element.

14 . The method according to claim 13 , wherein
the first metal element is a tungsten (W) element, and the second metal element is at least one of an aluminum (Al) element, a hafnium (Hf) element, or a zirconium (Zr) element.

15 . The method according to claim 11 , wherein the forming the first metal layer includes injecting metal atoms into the second substrate.

16 . The method according to claim 11 , wherein the forming the first metal layer includes forming a recess portion in the second substrate and burying the first metal layer in the recess portion.

17 . The method according to claim 11 ,
wherein the forming the first metal layer includes:
forming a first insulating film on the second substrate,
exposing the second substrate by forming a second opening in the first insulating film,
forming the first metal layer in the second opening, and
wherein the first plug is formed in the second opening.

18 . The method according to claim 11 , wherein the forming the first metal layer includes:
forming the first metal layer in the second substrate, forming a first insulating film on the second substrate and the first metal layer, exposing the first metal layer by forming a second opening in the first insulating film, and wherein the first plug is formed on the first metal layer exposed in the second opening.

19 . The method according to claim 11 , wherein the second metal layer is directly electrically connected to the first plug or the second metal layer is electrically connected to the first plug via the first metal layer.

20 . The method according to claim 11 , wherein the first opening is formed by using a gas containing an oxygen (O) element.

Assignees

• Kioxia Corp

Inventors

• Horiuchi Mitsunari

Classifications

• H10W90/792

  between multiple chips · CPC title

• H10W80/327

  characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers · CPC title

• H10W80/312

  characterised by the direct bonding of electrically conductive pads · CPC title

• H10W72/90

  Bond pads, in general · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title