Array substrate, and production method thereof, display panel, and display apparatus

Patent metadata

Field	Value
Publication number	US-11545510-B2
Application number	US-202017054823-A
Country	US
Kind code	B2
Filing date	Apr 16, 2020
Priority date	Jun 6, 2019
Publication date	Jan 3, 2023
Grant date	Jan 3, 2023

Abstract

This disclosure discloses an array substrate, and a production method, a display panel, and a display apparatus thereof. Particularly, this disclosure proposes a method of producing an array substrate, having the following steps: providing a substrate having a drive transistor region and a switch transistor region thereon; forming an preset layer for active layer on a side of the substrate; patterning the preset layer for active layer to form a drive active layer and a switch active layer, wherein an orthographic projection of the drive active layer on the substrate is located in the drive transistor region, an orthographic projection of the switch active layer on the substrate is located in the switch transistor region, and a carrier concentration in the drive active layer is less than a carrier concentration in the switch active layer.

First claim

What is claimed is:

1. A method of producing an array substrate, comprising
providing a substrate having a drive transistor region and a switch transistor region thereon;
forming a preset layer for active layer on a side of the substrate;
patterning the preset layer for active layer to form a drive active layer and a switch active layer, wherein an orthographic projection of the drive active layer on the substrate is located in the drive transistor region, an orthographic projection of the switch active layer on the substrate is located in the switch transistor region, and a carrier concentration in the drive active layer is less than a carrier concentration in the switch active layer,
wherein said patterning the present layer for active layer comprises the steps of:
etching the present layer for active layer into a first part and a second part by a patterning process using a photoresist, wherein an orthographic projection of the first part on the substrate located in the drive transistor region, and a first photoresist layer is retained on a surface of a side of the first part away from the substrate; an orthographic projection of the second part on the substrate is located in the switch transistor region, and a second photoresist layer is retained on a surface of a side of the second part away from the substrate; and a thickness of the second photoresist layer is greater than a thickness of the first photoresist layer;
removing the first photoresist layer by etching to expose the first part, and retaining a remaining thickness of the second photoresist layer on a surface of a side of the second part away from the substrate;
setting a carrier concentration in the first part to be less than a carrier concentration in the second part by carrier concentration differentiation treatment; and
removing the remaining thickness of the second photoresist layer, so that the first part forms the drive active layer and the second part forms the switch active layer.

2. The method according to claim 1 , wherein the carrier concentration differentiation treatment comprises:
performing annealing treatment on the first part or performing treatment on the first part by using plasma excited by an oxidative gas in an oxidative gas atmosphere to set a carrier concentration in the first part to be less than a carrier concentration in the second part.

3. The method according to claim 1 wherein
the step of etching the preset layer for active layer into a first part and a second part comprises:
coating a photoresist on a surface of a side of the preset layer for active layer away from the substrate;
exposing and developing the photoresist by using a half-tone mask plate to form a photoresist layer, the photoresist layer comprising: the first photoresist layer with the photoresist partly retained and the second photoresist layer with the photoresist completely retained;
performing etching treatment on the preset layer for active layer to remove the preset layer for active layer which is not covered by the photoresist layer to form the first part and the second part; and
the step of removing the first photoresist layer to expose the first part comprises dry etching.

4. The method according to claim 1 , wherein the carrier concentration differentiation treatment comprises:
setting a thickness of the first part to be less than a thickness of the second part by etching.

5. The method according to claim 4 , wherein the preset layer for active layer comprises two sublayers of which carrier concentrations are different, and the carrier concentration differentiation treatment further comprises:
removing a sublayer away from the substrate among the two sublayers in the first part by wet etching.

6. The method according to claim 1 , wherein the preset layer for active layer comprises two sublayers of which carrier concentrations are different, and a surface of the drive active layer away from the substrate and a surface of the switch active layer away from the substrate belong to the two sublayers, respectively.

7. The method according to claim 6 , wherein among the two sublayers, a carrier concentration in the sublayer closer to the substrate is less than a carrier concentration in the sublayer further away from the substrate.

8. The method according to claim 6 , wherein in the formed preset layer for active layer, the two sublayers are adjacent to each other and are different in material.

9. The method according to claim 6 , wherein the two sublayers are a first sublayer and a second sublayer, and the first sublayer is closer to the substrate than the second sublayer,
materials for forming the first sublayer comprise indium gallium zinc oxide, the first sublayer has a thickness of 10-50 nm, and a carrier concentration in the first sublayer is 10 15 -10 19 cm 2 V −1 s −1 ;
materials for forming the second sublayer comprise indium zinc oxide, the second sublayer has a thickness of 10-50 nm, and a carrier concentration in the second sublayer is 10 18 -10 20 cm 2 V −1 s −1 .

10. An array substrate,
wherein the array substrate comprises:
a substrate; and
a drive transistor and a switch transistor located on the substrate, wherein a carrier concentration in a drive active layer of the drive transistor is less than a carrier concentration in a switch active layer of the switch transistor,
wherein the switch active layer comprises a first sublayer and a second sublayer, wherein the first sublayer is closer to the substrate than the second sublayer, and a surface of the switch active layer away from the substrate belongs to the second sublayer, and
the drive active layer comprises a third sublayer formed in the same layer with the first sublayer, and a surface of the drive active layer away from the substrate belongs to the third sublayer,
wherein materials for forming the first sublayer/third sublayer comprise indium gallium zinc oxide, the first sublayer/third sublayer has a thickness of 10-50 nm, and a carrier concentration in the first sublayer/third sublayer is 10 15 -10 19 cm 2 V −1 s −1 ; materials for forming the second sublayer comprise indium zinc oxide, the second sublayer has a thickness of 10-50 nm, and a carrier concentration in the second sublayer in 10 18 -10 20 cm 2 V −1 s −1 .

11. The array substrate according to claim 10 , wherein a thickness of the drive active layer is less than a thickness of the switch active layer; or
at least one of the drive active layer and the switch active layer comprises a plurality of sublayers provided by lamination, wherein a number of the sublayers in the drive active layer is less than a number of the sublayers in the switch active layer; or
a concentration of carriers doped in the drive active layer is less than a concentration of the carriers doped in the switch active layer.

12. A display apparatus, comprising: the array substrate according to claim 10 .

Assignees

• Hefei Xinsheng Optoelectronics Technology Co Ltd
• Boe Technology Group Co Ltd
• Beijing Boe Technology Dev Co Ltd

Inventors

• Song Wei
• Zhao Ce
• Ding Yuankui
• Wang Ming
• Hu Yingbin
• Wang Qinghe
• Li Wei
• Ni Liusong

Classifications

• H10P14/3434

  being oxide semiconductor materials (Group IIB-VIA semiconductor materials H10P14/3424) · CPC title

• H01L29/78696

  Electricity · mapped topic

• H01L27/127 Primary

  Electricity · mapped topic

• H01L29/66969

  Electricity · mapped topic

• H01L21/02565

  Electricity · mapped topic