Thin film transistors, arrays substrates, and manufacturing methods

Patent metadata

Field	Value
Publication number	US-10153304-B2
Application number	US-201615305082-A
Country	US
Kind code	B2
Filing date	Jul 20, 2016
Priority date	Jul 8, 2016
Publication date	Dec 11, 2018
Grant date	Dec 11, 2018

Abstract

The present disclosure relates to a TFT includes an active layer formed on a substrate, wherein the active layer includes a first semiconductor layer and a second semiconductor layer stacked together. The first semiconductor layer is made by Indium gallium zinc oxide (IGZO) having an atomic ratio In/(Ga+Zn) smaller than 50%, and the second semiconductor layer is made by IGZO having the atomic ratio In/(Ga+Zn) greater than 55%. The present disclosure also includes an array substrate having the TFT and the manufacturing method thereof. The array substrate may be adopted in LCD or OLED. The TFT adopts two layers of IGZO semiconductor materials to be the semiconductor of the active layer. Not only the demand toward the TFT characteristics may be satisfied, but also the carrier mobility rate of the IGZO active layer may be enhanced.

First claim

What is claimed is:

1. A thin film transistor (TFT), comprising:
an active layer formed on a substrate, wherein the active layer comprises a first semiconductor layer and a second semiconductor layer stacked together, the first semiconductor layer is made by Indium gallium zinc oxide (IGZO) having an atomic ratio In/(Ga+Zn) smaller than 50%, and the second semiconductor layer is made by IGZO having the atomic ratio In/(Ga+Zn) greater than 55%;
wherein an oxygen protection layer covers the second semiconductor layer;
wherein the TFT further comprises a gate electrode, a source electrode, and a drain electrode, wherein a buffer layer is formed on the substrate, the first semiconductor layer and the second semiconductor layer are formed on the buffer layer in sequence, a gate insulation layer and the gate electrode are formed on the active layer in sequence, an insulation dielectric layer is arranged on the gate electrode, and the insulation dielectric layer covers the substrate, the source electrode and the drain electrode are formed on the insulation dielectric layer, and the source electrode and the drain electrode respectively connects to the active layer via at least one through hole within the insulation dielectric layer;
wherein the oxygen protection layer covers a middle area of the active layer, and the active layer is exposed by two sides of the oxygen protection layer; and

the exposed first semiconductor layer and the second semiconductor layer of the active layer are transformed into conductors by applying an ion injection process or a plasma bombard process, wherein one end is formed as a source connection portion, and the other end is formed as a drain connection portion, the source electrode connects to the source connection portion via the through hole configured within the insulation dielectric layer, and the drain electrode connects to the drain connection portion via the through hole configured within the insulation dielectric layer.

2. The TFT as claimed in claim 1 , wherein the first semiconductor layer is made by IGZO having the atomic ratio In/(Ga+Zn) in a range from 40 to 50%.

3. The TFT as claimed in claim 1 , wherein the second semiconductor layer is made by IGZO having the atomic ratio In/(Ga+Zn) in a range from 55 to 60%.

4. A TFT array substrate, comprising:
a glass substrate and a TFT arranged on the glass substrate, wherein the TFT comprises an active layer formed on a substrate, wherein the active layer comprises a first semiconductor layer and a second semiconductor layer stacked together, the first semiconductor layer is made by Indium gallium zinc oxide (IGZO) having an atomic ratio In/(Ga+Zn) smaller than 50%, and the second semiconductor layer is made by IGZO having the atomic ratio In/(Ga+Zn) greater than 55%;
wherein an oxygen protection layer covers the second semiconductor layer;
wherein the TFT further comprises a gate electrode, a source electrode, and a drain electrode, wherein a buffer layer is formed on the substrate, the first semiconductor layer and the second semiconductor layer are formed on the buffer layer in sequence, a gate insulation layer and the gate electrode are formed on the active layer in sequence, an insulation dielectric layer is arranged on the gate electrode, and the insulation dielectric layer covers the substrate, the source electrode and the drain electrode are formed on the insulation dielectric layer, and the source electrode and the drain electrode respectively connects to the active layer via at least one through hole within the insulation dielectric layer;
wherein the oxygen protection layer covers a middle area of the active layer, and the active layer is exposed by two sides of the oxygen protection layer; and
the exposed first semiconductor layer and the second semiconductor layer of the active layer are transformed into a conductor by applying an ion injection process or a plasma bombard process, wherein one end is formed as a source connection portion, and the other end is formed as a drain connection portion, the source electrode connects to the source connection portion via the through hole configured within the insulation dielectric layer, and the drain electrode connects to the drain connection portion via the through hole configured within the insulation dielectric layer.

5. The TFT array substrate as claimed in claim 4 , wherein the first semiconductor layer is made by IGZO having the atomic ratio In/(Ga+Zn) in a range from 40 to 50%.

6. The TFT array substrate as claimed in claim 4 , wherein the second semiconductor layer is made by IGZO having the atomic ratio In/(Ga+Zn) in a range from 55 to 60%.

7. A manufacturing method of TFT array substrates, comprising:
S 1 : providing a glass substrate and forming a buffer layer on the glass substrate;
S 2 : forming a first semiconductor layer and a second semiconductor layer on the buffer layer in sequence, wherein an active layer comprises the first semiconductor layer and the second semiconductor layer stacked together, the first semiconductor layer is made by Indium gallium zinc oxide (IGZO) having an atomic ratio In/(Ga+Zn) smaller than 50%, and the second semiconductor layer is made by IGZO having the atomic ratio In/(Ga+Zn) greater than 55%;
S 3 : adopting a first masking process to etch the first semiconductor layer and the second semiconductor layer to form the patterned active layer, the active layer comprises the first semiconductor layer and the second semiconductor layer stacked in sequence;
S 4 : forming a gate insulating layer and a gate electrode layer on the glass substrate having the active layer in sequence;
S 5 : adopting a second masking process to etch the gate insulation layer and the gate electrode layer to form the patterned gate insulation layer and gate electrode;
S 6 : forming an insulation dielectric layer on the gate electrode, and covering the glass substrate by the insulation dielectric layer;
S 7 : adopting a third masking process to form a through hole within the insulation dielectric layer;
S 8 : forming a metallic conductive layer on the insulation dielectric layer;
S 9 : adopting a fourth masking process to etch the metallic conductive layer to form a patterned source electrode and a patterned drain electrode, the source electrode and the drain electrode respectively connects to the active layer via the through hole within the insulation dielectric layer;
wherein the step S 5 further comprises:
Step S 51 : adopting a top gate self-aligned process to perform an etching process to form the gate insulation layer and the gate electrode; and
Step S 52 : adopting an ion injection process or a plasma bombard process to transform two ends of the first semiconductor layer and the second semiconductor layer to be conductors, wherein one end is formed as a source connection portion, and the other end is formed as a drain connection portion.

8. The TFT array substrate as claimed in claim 7 , wherein the first semiconductor layer is made by IGZO having the atomic ratio In/(Ga+Zn) in a range from 40 to 50%.

9. The TFT array substrate as claimed in claim 7 , wherein the second semiconductor layer is made by IGZO having the atomic ratio In/(Ga+Zn) in a range from 55 to 60%.

10. The TFT array substrate as claimed in claim 7 , wherein the step S 2 further comprises covering the second semiconductor layer by an oxygen protection layer.

Assignees

• Wuhan China Star Optoelectronics Technology Co Ltd
• Wuhan China Star Optoelectronics Technology Co Ltd

Inventors

• Qin Fang

Classifications

• H10W74/137

  the encapsulations being directly on the semiconductor body (H10W74/134 takes precedence) · CPC title

• H01L29/7869

  Electricity · mapped topic

• H01L27/1225 Primary

  Electricity · mapped topic

• H01L27/12

  Electricity · mapped topic

• H01L29/06

  Electricity · mapped topic