TFT arrangement structure comprising stacked dual TFT's

Patent metadata

Field	Value
Publication number	US-9768203-B2
Application number	US-201514770089-A
Country	US
Kind code	B2
Filing date	May 22, 2015
Priority date	Apr 14, 2015
Publication date	Sep 19, 2017
Grant date	Sep 19, 2017

Abstract

The present invention provides a TFT arrangement structure, comprising a first thin film transistor (T 1 ) and a second thin film transistor (T 2 ) controlled by the same control signal line; the first active layer (SC 1 ) of the first thin film transistor (T 1 ) and the second active layer (SC 2 ) of the second thin film transistor (T 2 ) are at different layers, and positioned to stack up in space, and the first source (S 1 ) and the first drain (D 1 ) of the first thin film transistor (T 1 ) contact the first active layer (SC 1 ), and the second source (S 2 ) and the second drain (D 2 ) of the second thin film transistor (T 2 ) contact the second active layer (SC 2 ); the bottom gate layer (Bottom Gate) of the first thin film transistor (T 1 ) is positioned under the first active layer (SC 1 ), and the top gate layer (Top Gate) of the second thin film transistor (T 2 ) is above the second active layer (SC 2 ). The TFT arrangement structure can reduce the space of the circuit arrangement to increase the flexibility of the circuit arrangement and satisfy the demands of the narrow frame and high resolution to the display panel.

First claim

What is claimed is:

1. A thin-film transistor (TFT) arrangement structure, comprising a first thin film transistor and a second thin film transistor controlled by the same control signal line;
wherein the first thin film transistor comprises a bottom gate layer, a first active layer, a first source and a first drain, and the second thin film transistor comprises a second active layer, a second source, a second drain and a top gate layer;
the first active layer and the second active layer are at different layers, and positioned to stack up in a vertical direction in space, and the first source and the first drain contact the first active layer, and the second source and the second drain contact the second active layer; and
the bottom gate layer is positioned under the first active layer in the vertical direction, and the top gate layer is above the second active layer in the vertical direction, and both the bottom gate layer and the top gate layer are electrically coupled to the control signal line to respectively control on and off of the first thin film transistor and the second thin film transistor;
wherein the bottom gate layer and the top gate layer are separate and spaced from each other by the stack of the first active layer and the second active layer and are respectively located at opposite sides of the stack of the first active layer and the second active layer;
wherein the first active layer of the first thin film transistor has a middle portion and two end portions extending from the middle portion along a first horizontal linear axis in opposite directions; the second active layer has a middle portion and two end portions extending from the middle portion along a second horizontal linear axis in opposite directions, wherein the first and second horizontal linear axes are angularly shifted away from each other about the vertical direction and are angularly spaced from each other;
wherein the bottom gate layer of the first thin film transistor extends horizontally along a third horizontal linear axis that is angularly shifted away from the first horizontal linear axis about the vertical direction and is angularly spaced from the first horizontal linear axis; and the top gate layer of the second thin film transistor extends horizontally along a fourth horizontal linear axis that is angularly shifted away from the second horizontal linear axis about the vertical direction and is angularly spaced from the second horizontal linear axis, wherein the third and fourth horizontal linear axes are substantially coincident with each other and the third and fourth horizontal linear axes are angularly spaced from the first horizontal linear axis and are also angularly spaced from the second horizontal linear axis, such that the first horizontal linear axis, the second horizontal linear axis, and the third and fourth horizontal linear axes are angularly spaced from one another.

2. The TFT arrangement structure according to claim 1 , further comprising a substrate, a first insulation layer, a passivation layer and a second insulation layer; the first source, the first drain and the second source, the second drain are positioned at the same layer or at different layers.

3. The TFT arrangement structure according to claim 2 , wherein the bottom gate layer is positioned on the substrate, and the first insulation layer is positioned on the bottom gate layer and the substrate, and the first active layer is positioned on the first insulation layer, and the passivation layer is positioned on the first active layer and the first insulation layer, and the first source and the first drain are positioned on the passivation layer and respectively contact the two end portions of the first active layer through passivation layer via holes, and the second active layer is positioned on the passivation layer, and the second source and the second drain are positioned on the passivation layer and respectively cover the two end portions of the second active layer, and the second insulation layer is positioned on the first source, the first drain, the second active layer, the second source, the second drain and the passivation layer, and the top gate layer is positioned on the second insulation layer.

4. The TFT arrangement structure according to claim 2 , wherein the bottom gate layer is positioned on the substrate, and the first insulation layer is positioned on the bottom gate layer and the substrate, and the first active layer is positioned on the first insulation layer, and the first source and the first drain are positioned on the first insulation layer and respectively cover the two end portions of the first active layer, and the passivation layer is positioned on the first active layer, the first source, the first drain and the first insulation layer, and the second active layer is positioned on the passivation layer, and the second source and the second drain are positioned on the passivation layer and respectively cover the two end portions of the second active layer, and the second insulation layer is positioned on the second active layer, the second source, the second drain and the passivation layer, and the top gate layer is positioned on the second insulation layer.

5. The TFT arrangement structure according to claim 2 , wherein material of the bottom gate layer, the first source, the first drain, the second source, the second drain and the top gate layer is a stack combination of one or more of molybdenum, titanium, aluminum and copper.

6. The TFT arrangement structure according to claim 2 , wherein material of the first active layer and the second active layer is one of amorphous silicon based semiconductor, polysilicon based semiconductor and Zinc Oxide based semiconductor.

7. The TFT arrangement structure according to claim 2 , wherein material of the first insulation layer and the second insulation layer is Silicon Nitride, Silicon Oxide or a combination of the two.

8. The TFT arrangement structure according to claim 6 , wherein the first active layer and the second active layer are both n-type semiconductor or both p-type semiconductor.

9. The TFT arrangement structure according to claim 6 , wherein one of the first active layer and the second active layer is p-type semiconductor and the other is n-type semiconductor.

10. A thin-film transistor (TFT) arrangement structure, comprising a first thin film transistor and a second thin film transistor controlled by the same control signal line;
the first thin film transistor comprises a bottom gate layer, a first active layer, a first source and a first drain, and the second thin film transistor comprises a second active layer, a second source, a second drain and a top gate layer;
the first active layer and the second active layer are at different layers, and positioned to stack up in a vertical direction in space, and the first source and the first drain contact the first active layer, and the second source and the second drain contact the second active layer;
the bottom gate layer is positioned under the first active layer in the vertical direction, and the top gate layer is above the second active layer in the vertical direction, and both the bottom gate layer and the top gate layer are electrically coupled to the control signal line to respectively control on and off of the first thin film transistor and the second thin film transistor;
wherein the bottom gate layer and the top gate layer are separate and spaced from each other by the stack of the first active layer and the second active layer and are respectively located at opposite sides of the stack of the first active layer and the second active layer;
wherein the first active layer of the first thin film transistor has a middle port

Assignees

• Shenzhen China Star Optoelect

Inventors

• Han Baixiang
• Shi Longqiang

Classifications

• H01L27/124

  Electricity · mapped topic

• H01L27/1225

  Electricity · mapped topic

• H01L29/22

  Electricity · mapped topic

• H01L27/1222

  Electricity · mapped topic

• H01L27/1251 Primary

  Electricity · mapped topic