Crystalline layer stack for forming conductive layers in a three-dimensional memory structure

Patent metadata

Field	Value
Publication number	US-9870945-B2
Application number	US-201514643280-A
Country	US
Kind code	B2
Filing date	Mar 10, 2015
Priority date	Mar 10, 2015
Publication date	Jan 16, 2018
Grant date	Jan 16, 2018

Abstract

A stack of alternating layers comprising first epitaxial semiconductor layers and second epitaxial semiconductor layers is formed over a single crystalline substrate. The first and second epitaxial semiconductor layers are in epitaxial alignment with a crystal structure of the single crystalline substrate. The first epitaxial semiconductor layers include a first single crystalline semiconductor material, and the second epitaxial semiconductor layers include a second single crystalline semiconductor material that is different from the first single crystalline semiconductor material. A backside contact opening is formed through the stack, and backside cavities are formed by removing the first epitaxial semiconductor layers selective to the second epitaxial semiconductor layers. A stack of alternating layers including insulating layers and electrically conductive layers is formed. Each insulating layer contains a dielectric material portion deposited within a respective backside cavity. Each electrically conductive layer contains a material from a portion of a respective second epitaxial semiconductor layer.

First claim

What is claimed is:

1. A monolithic three-dimensional memory device, comprising:
a stack of layers comprising insulating layers and electrically conductive layers located over a substrate;
a memory opening extending through an entirety of the stack of layers and defining a continuous set of sidewalls of the stack of layers; and
a memory stack structure located in the memory opening and extending through the stack of layers and comprising, from outside to inside, a memory film and a polysilicon vertical semiconductor channel,
wherein each of the electrically conductive layers comprises at least one of a single crystalline doped semiconductor material portion and a single crystalline metal-semiconductor alloy portion; and
wherein each electrically conductive layer within the stack of layers includes a respective hole therethrough that coincides entirely with the memory opening at a respective level, and each electrically conductive layer completely laterally surrounds and completely encircles the memory stack structure.

2. The monolithic three-dimensional memory device of claim 1 , wherein:
each of the electrically conductive layers comprises the single crystalline doped semiconductor material portion;
the substrate comprises a single crystalline semiconductor material layer having a same crystal structure as the single crystalline doped semiconductor material portions; and
spatial orientations of crystallographic axes coincide between each of the single crystalline doped semiconductor material portions and the single crystalline semiconductor material layer for each Miller index.

3. The monolithic three-dimensional memory device of claim 2 , wherein the single crystalline doped semiconductor material portions comprise single crystalline doped silicon portions.

4. The monolithic three-dimensional memory device of claim 2 , wherein each of the single crystalline doped semiconductor material portions contacts an outer sidewall of the memory stack structure.

5. The monolithic three-dimensional memory device of claim 2 , wherein each of the electrically conductive layers consists entirely of a respective single crystalline doped semiconductor material portion.

6. The monolithic three-dimensional memory device of claim 5 , wherein each of the insulating layers in the stack of layers comprises at least one cavity embedded therein.

7. The monolithic three-dimensional memory device of claim 5 , wherein an entire volume within surfaces of each of the insulating layers is filled with a dielectric material.

8. The monolithic three-dimensional memory device of claim 2 , further comprising:
a backside contact via structure extending through the stack of layers and contacting a portion of the substrate; and
an insulating spacer laterally surrounding the backside contact via structure,
wherein each of the electrically conductive layers contacts an outer sidewall of the insulating spacer.

9. The monolithic three-dimensional memory device of claim 2 , wherein each electrically conductive layer comprises a metallic material portion laterally contacting a respective single crystalline doped semiconductor material portion.

10. The monolithic three-dimensional memory device of claim 9 , wherein the metallic material portion comprises the single crystalline metal-semiconductor alloy portion of the single crystalline doped semiconductor material portions and a metal.

11. The monolithic three-dimensional memory device of claim 9 , wherein each metallic material portion is a single crystalline metal silicide portion.

12. The monolithic three-dimensional memory device of claim 9 , wherein the metallic material portion comprises:
a metallic liner portion comprising a metal nitride or a metal carbide and contacting the respective single crystalline doped semiconductor material portion; and
a metal fill portion comprising an elemental metal or an intermetallic alloy of at least two elemental metals and laterally spaced from the respective single crystalline doped semiconductor material portion by the metallic liner portion.

13. The monolithic three-dimensional memory device of claim 1 , wherein:
the monolithic three-dimensional memory device is a vertical NAND memory device; and
one or more of the electrically conductive layers comprise, or are electrically connected to, a respective word line of the vertical NAND memory device.

14. The monolithic three-dimensional memory device of claim 13 , wherein the electrically conductive layers comprises a source select level gate electrode underlying the at least one word line.

15. The monolithic three-dimensional memory device of claim 14 , further comprising an epitaxial pedestal channel region located at a bottom portion of the memory stack structure and laterally surrounded by the source select level gate electrode, wherein:
the single crystalline doped semiconductor material portions and the epitaxial pedestal channel region have a same crystal structure; and
spatial orientations of crystallographic axes coincide between the single crystalline doped semiconductor material portion and the epitaxial pedestal channel region for each Miller index.

16. The monolithic three-dimensional memory device of claim 13 , wherein:
the substrate comprises a silicon substrate;
the NAND memory device comprises an array of monolithic three-dimensional NAND strings over the silicon substrate;
at least one memory cell in the first device level of the three-dimensional array of NAND strings is located over another memory cell in the second device level of the three-dimensional array of NAND strings;
the silicon substrate contains an integrated circuit comprising a driver circuit for the memory device located thereon; and
the three-dimensional array of NAND strings comprises:
a plurality of the vertical semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the semiconductor substrate;
a plurality of memory films containing charge storage elements, each charge storage element located adjacent to a respective one of the plurality of vertical semiconductor channels; and
a plurality of the electrically conductive layers comprising a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate, the plurality of control gate electrodes comprise at least a first control gate electrode located in the first device level and a second control gate electrode located in the second device level.

17. The monolithic three-dimensional memory device of claim 1 , wherein each electrically conductive layer within the stack of layers physically contacts a respective portion of an outer sidewall of the memory opening.

18. The monolithic three-dimensional memory device of claim 1 , wherein each insulating layer within the stack of layers includes a respective hole that coincides entirely with the memory opening at a respective level, and laterally surrounds and encircles the memory stack structure.

19. The monolithic three-dimensional memory device of claim 18 , wherein each insulating layer within the stack of layers contacts a respective portion of an outer sidewall of the memory opening.

20. The monolithic three-dimensional memory device of claim 1 , wherein an entirety of outer sidewalls of the memory stack structure at levels of the stack of layers is in physical contact with a set of surfaces consisting of sidewalls of the electrically c

Assignees

• Sandisk Technologies Inc
• Sandisk Technologies Llc

Inventors

• Pachamuthu Jayavel
• Baenninger Matthias
• Shi Stephen
• Alsmeier Johann
• Chien Henry

Classifications

• H10W20/072

  of dielectric parts comprising air gaps · CPC title

• H10W20/46

  comprising air gaps · CPC title

• H10W20/056 Primary

  by filling conductive material into holes, grooves or trenches · CPC title

• H01L21/28282

  Electricity · mapped topic

• H01L21/76883 Primary

  Electricity · mapped topic