Identifying load-hit-store conflicts

Patent metadata

Field	Value
Publication number	US-9229746-B2
Application number	US-201314109996-A
Country	US
Kind code	B2
Filing date	Dec 18, 2013
Priority date	Sep 12, 2012
Publication date	Jan 5, 2016
Grant date	Jan 5, 2016

Abstract

A computing device identifies a load instruction and store instruction pair that causes a load-hit-store conflict. A processor tags a first load instruction that instructs the processor to load a first data set from memory. The processor stores an address at which the first load instruction is located in memory in a special purpose register. The processor determines where the first load instruction has a load-hit-store conflict with a first store instruction. If the processor determines the first load instruction has a load-hit store conflict with the first store instruction, the processor stores an address at which the first data set is located in memory in a second special purpose register, tags the first data set being stored by the first store instruction, stores an address at which the first store instruction is located in memory in a third special purpose register and increases a conflict counter.

First claim

What is claimed is:

1. A method for identification of a load instruction and store instruction pair that causes a load-hit-store conflict, comprising the steps of:
a processor tagging a first load instruction, wherein the first load instruction instructs the processor to load a first data set from a memory;
the processor storing in a first special purpose register an address at which the first load instruction is located in memory;
the processor determining whether the first load instruction has a load-hit-store conflict with a first store instruction, wherein the load-hit-store conflict occurs when the first load instruction instructs the processor to load the first data from memory before the first data set has been stored into memory by the first store instruction;
responsive to determining the first load instruction has a load-hit-store conflict with the first store instruction, the processor storing an address at which the first data set is located in memory in a second special purpose register, the processor tagging the first data set being stored by the first store instruction, the processor storing an address at which the first store instruction is located in memory in a third special purpose register, and the processor increasing a conflict counter.

2. The method of claim 1 , wherein the step of the processor increasing the conflict counter further comprises the processor generating an interrupt and locking all special purpose registers when the conflict counter surpasses a pre-set threshold value.

3. The method of claim 1 , further comprising the steps of:
the processor tagging a second load instruction that instructs the processor to load a second data set from a memory;
the processor storing an address at which the second load instruction is located in memory in the first special purpose register;
the processor determining whether the second load instruction has a load-hit-store conflict with a second store instruction, wherein the load-hit-store conflict occurs when the second load instruction instructs the processor to load the second data set from memory before the second data set has been stored into memory by the second store instruction;
responsive to determining the second load instruction does not have a load-hit-store conflict with the second store instruction, the processor deleting the address at which the second load instruction is located in memory from the first special purpose register.

Assignees

• IBM

Inventors

• Indukuru Venkat R
• Mericas Alexander E
• Sadasivam Satish K
• Valluri Madhavi G

Classifications

• G06F9/3834 Primary

  Maintaining memory consistency · CPC title

• G06F9/44552 Primary

  Conflict resolution, i.e. enabling coexistence of conflicting executables · CPC title