Processor core including pre-issue load-hit-store (LHS) hazard prediction to reduce rejection of load instructions

Patent metadata

Field	Value
Publication number	US-10209995-B2
Application number	US-201414522811-A
Country	US
Kind code	B2
Filing date	Oct 24, 2014
Priority date	Oct 24, 2014
Publication date	Feb 19, 2019
Grant date	Feb 19, 2019

Abstract

A processor core supporting out-of-order execution (OOE) includes load-hit-store (LHS) hazard prediction at the instruction execution phase, reducing load instruction rejections and queue flushes at the dispatch phase. The instruction dispatch unit (IDU) detects likely LHS hazards by generating entries for pending stores in a LHS detection table. The entries in the table contain an address field (generally the immediate field) of the store instruction and the register number of the store. The IDU compares the address field and register number for each load with entries in the table to determine if a likely LHS hazard exists and if an LHS hazard is detected, the load is dispatched to the issue queue of the load-store unit (LSU) with a tag corresponding to the matching store instruction, causing the LSU to dispatch the load only after the corresponding store has been dispatched for execution.

First claim

What is claimed is:

1. A processor core, comprising:
one or more hardware facilities including execution units for executing instructions, including a load-store unit for loading and storing data values operated on by the instructions, wherein the instructions include load instructions and store instructions of an instruction stream;
an instruction fetch unit for fetching the instructions;
an instruction dispatch unit for dispatching the instructions to issue queues corresponding to the execution units according to a type of the instructions, wherein the instruction dispatch unit includes control logic that detects each store instruction of the instruction stream during dispatching of the instructions, wherein the store instructions are instructions that write store values to locations specified by corresponding store addresses, and wherein the instruction dispatch unit, for each detected store instruction stores store address information associated with each detected store instruction by generating a corresponding new entry containing the associated store address information, a type value indicating a type of addressing used for a corresponding one of the store instructions, a thread number of the corresponding one of the store instructions and an itag identifying the corresponding one of the store instructions in a load-hit-store detection table internal to the processor core and further dispatches each detected store instruction to one of the issue queues, wherein the load-hit-store detection table is a storage separate from the issue queues, wherein the control logic, further responsive to detecting each store instruction and as the detected store instruction is being dispatched, first compares address information associated with the detected store instruction with entries in the load-hit-store detection table to determine whether or not a first matching entry exists matching the address information associated with the detected store instruction, wherein the control logic, responsive to determining that the first matching entry exists, invalidates the first matching entry, wherein the control logic further includes control logic that detects each load instruction of the instruction stream during the dispatching of the instructions and, responsive to detecting each load instruction and prior to dispatch of the load instruction, second compares store address information of entries in the load-hit-store detection table with load address information of each load instruction to determine whether or not a second matching entry in the load-hit-store detection table indicates that the load instruction is a likely load-hit-store hazard, whereby each load instruction detected by the control logic is matched against entries in the load-hit-store detection table to determine whether or not the detected load instruction is a likely load-hit-store hazard, wherein the control logic matches the entries by matching one or more selected fields of the store address information stored within the entries by selecting the selected fields according to the stored type value of the entries and wherein the control logic, responsive to determining that the load instruction is a likely load-hit-store hazard, identifies the load instruction determined to be a likely load-hit-store hazard to the load-store unit by forwarding the itag stored in the second matching entry in the load-hit-store detection table to the load-store unit along with the load instruction.

2. The processor core of claim 1 , wherein the control logic, responsive to determining that the detected load instruction is not a likely load-hit-store hazard, dispatches the detected load instruction to the one of the issue queues without a corresponding itag.

3. The processor core of claim 2 , wherein the store address information stored in the new entry in the load-hit-store detection table is one or both of an immediate field of the corresponding one of the store instructions and one or more base register numbers of the corresponding one of the store instructions.

4. The processor core of claim 2 , wherein the load-store unit examines a next entry of the one of the issue queues to determine whether or not a next instruction is a next load instruction having a corresponding itag, and wherein the load-store unit, responsive to determining that the next instruction is not the next load instruction having a corresponding itag, processes the next entry for execution by the load-store unit, wherein the load-store unit examines the next entry of the one of the issue queues to determine whether or not the next instruction is a next store instruction, wherein the load-store unit, responsive to determining that the next instruction is the next store instruction, examines the next entry of the one of the issue queues to determine whether a second load instruction having a corresponding itag matching an itag of the next store instruction is present, wherein the load-store unit, responsive to determining that the next instruction is the next store instruction, processes the next store instruction for execution by the load-store unit, and wherein the load-store unit, responsive to determining that the second load instruction having a corresponding itag matching the itag of the next store instruction is present, processes the second load instruction for execution by the load-store unit subsequent to processing the next store instruction.

5. A processing system, comprising:
a memory for storing program instructions and data values; and
a processor coupled to the memory for executing the program instructions to operate on the data values, wherein the processor comprises one or more hardware facilities including execution units for executing the program instructions including a load-store unit for loading and storing the data values operated on by the program instructions, wherein the program instructions include load instructions and store instructions of an instruction stream, an instruction fetch unit for fetching the program instructions, an instruction dispatch unit for dispatching the program instructions to issue queues corresponding to the execution units according to a type of the instructions, wherein the instruction dispatch unit includes control logic that detects each store instruction of the instruction stream during dispatching of the instructions, wherein the store instructions are instructions that write store values to locations specified by corresponding store addresses, and wherein the instruction dispatch unit, for each detected store instruction stores store address information associated with each detected store instruction by generating a corresponding new entry containing the associated store address information, a type value indicating a type of addressing used for a corresponding one of the store instructions, a thread number of the corresponding one of the store instructions and an itag identifying the corresponding one of the store instructions in a load-hit-store detection table internal to the processor core and further dispatches each detected store instruction to one of the issue queues, wherein the load-hit-store detection table is a storage separate from the issue queues, wherein the control logic, further responsive to detecting each store instruction and as the detected store instruction is being dispatched, first compares address information associated with the detected store instruction with entries in the load-hit-store detection table to determine whether or not a first matching entry exists matching the address information associated with the detected store instruction, wherein the control logic, responsive to determining that the first matching entry exists, invalidates the first matching entry, wherein the control logic further includes control logic that detects each load instruc

Assignees

• IBM

Inventors

• Chadha Sundeep
• Eickemeyer Richard James
• Griswell Jr John Barry
• Nguyen Dung Quoc

Classifications

• G06F9/3838 Primary

  Dependency mechanisms, e.g. register scoreboarding · CPC title

• G06F9/3834

  Maintaining memory consistency · CPC title