Hazard detection of out-of-order execution of load and store instructions in processors without using real addresses

Patent metadata

Field	Value
Publication number	US-10417002-B2
Application number	US-201715726538-A
Country	US
Kind code	B2
Filing date	Oct 6, 2017
Priority date	Oct 6, 2017
Publication date	Sep 17, 2019
Grant date	Sep 17, 2019

Abstract

Technical solutions are described for hazard detection of out-of-order execution of load and store instructions without using real addresses in a processing unit. An example includes an out-of-order load-store unit (LSU) for transferring data between memory and registers. The LSU detects a store-hit-load (SHL) in an out-of-order execution of instructions based only on effective addresses by: determining an effective address associated with a store instruction; determining whether a load instruction entry using said effective address is present in a load reorder queue; and indicating that a SHL has been detected based at least in part on determining that load instruction entry using said effective address is present in the load reorder queue. The LSU, in response to detecting the SHL, flushes instructions starting from a load instruction corresponding to the load instruction entry.

First claim

What is claimed is:

1. A processing unit for executing one or more instructions, the processing unit comprising:
a load-store unit for transferring data between memory and registers, the load-store unit configured to:
detect a store-hit-load (SHL) in an out-of-order execution of instructions based only on effective addresses by:
determining an effective address associated with a store instruction;
determining whether a load instruction entry using said effective address is present in a load reorder queue; and
indicating that a SHL has been detected based at least in part on determining that load instruction entry using said effective address is present in the load reorder queue; and

in response to detecting the SHL, flush instructions starting from a load instruction corresponding to the load instruction entry;
detect a load-hit-load (LHL) in the out-of-order execution of instructions based only on the effective addresses, wherein the load instruction is a first load instruction, the load instruction entry is a first load instruction entry, and detecting the LHL comprises:
determining the effective address associated with the first load instruction;
determining whether a second load instruction entry using said effective address is present in the load reorder queue; and
indicating that a LHL has been detected based at least in part on determining that second load instruction entry using said effective address is present in the load reorder queue; and

in response to detecting the LHL, flush instructions starting from the second load instruction.

2. The processing unit of claim 1 , wherein the load-store unit is further configured to maintain the load instruction entry for the load instruction in the load reorder queue until completion of the load instruction.

3. The processing unit of claim 1 , wherein determining whether the load instruction entry using said effective address is present in the load reorder queue further comprises:
determining whether an effective real table index for the load instruction entry and the store instruction match each other.

4. The processing unit of claim 1 , wherein determining whether the second load instruction entry using said effective address is present in the load reorder queue further comprises: determining whether an effective real table index for the first load instruction entry and the second load instruction match each other.

5. The processing unit of claim 1 , wherein flushing instructions starting from the load instruction corresponding to the load instruction entry comprises:
sending a flush message to an instruction fetch unit that comprises an identifier of the load instruction, wherein the flushing comprises relinquishing launch of the instructions fetched by the instruction fetch unit starting from the load instruction.

6. The processing unit of claim 1 , wherein the load reorder queue comprises a number of partitions, one partition for each load instruction issued concurrently by the load-store unit.

7. A computer-implemented method for executing one or more out-of-order instructions by a processing unit, the method comprising:
detecting, by a load-store unit, a store-hit-load (SHL) in an out-of-order execution of instructions based only on effective addresses by:
determining an effective address associated with a store instruction; and
determining whether a load instruction entry using said effective address is present in a load reorder queue; and
indicating that a SHL has been detected based at least in part on determining that load instruction entry using said effective address is present in the load reorder queue; and
in response to detecting the SHL, sending, by the load-store unit, a flush message for instructions starting from a load instruction corresponding to the load instruction entry;

detecting, by load-store unit, a load-hit-load (LHL) in the out-of-order execution of instructions based only on the effective addresses by:
determining the effective address associated with the first load instruction; and
determining whether a second load instruction entry using said effective address is present in the load reorder queue; and
indicating that a LHL has been detected based at least in part on determining that second load instruction entry using said effective address is present in the load reorder queue; and
in response to detecting the LHL, flushing instructions starting from the second load instruction.

8. The computer-implemented method of claim 7 , further comprising maintaining, by the load-store unit, the load instruction entry for the load instruction in the load reorder queue until completion of the load instruction.

9. The computer-implemented method of claim 7 , wherein determining whether the load instruction entry using said effective address is present in the load reorder queue further comprises: determining whether effective real table index for the load instruction entry and the store instruction match each other.

10. The computer-implemented method of claim 7 , wherein determining whether the first load instruction entry using said effective address is present in the load reorder queue further comprises: determining whether effective real table index for the first load instruction entry and the second load instruction match each other.

11. The computer-implemented method of claim 7 , wherein flushing instructions starting from the load instruction corresponding to the load instruction entry comprises:
sending a flush message to an instruction fetch unit that comprises an identifier of the load instruction, wherein the flushing comprises relinquishing launch of the instructions fetched by the instruction fetch unit starting from the load instruction.

12. The computer-implemented method of claim 7 , wherein the load reorder queue comprises a number of partitions, one partition for each load instruction issued concurrently by the load-store unit.

13. A computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to cause the processor to perform operations comprising:
detecting, by a load-store unit, a store-hit-load (SHL) in an out-of-order execution of instructions based only on effective addresses by:
determining an effective address associated with a store instruction; and
determining whether a load instruction entry using said effective address is present in a load reorder queue; and
indicating that a SHL has been detected based at least in part on determining that load instruction entry using said effective address is present in the load reorder queue; and

in response to detecting the SHL, sending, by the load-store unit, a flush message for instructions starting from a load instruction corresponding to the load instruction entry;
detecting, by load-store unit, a load-hit-load (LHL) in the out-of-order execution of instructions based only on the effective addresses by:
determining the effective address associated with the first load instruction; and
determining whether a second load instruction entry using said effective address is present in the load reorder queue; and
indicating that a LHL has been detected based at least in part on determining that second load instruction entry using said effective address is present in the load reorder queue; and

in response to detecting the LHL, flushing instructions starting from the second load instruction.

14. The computer program product of claim 13 , wherein determining whether the load instruction entry using said effective address is present in the load reorder

Assignees

• IBM

Inventors

• Lloyd Bryan
• Sinharoy Balaram
• Tung Shih-Hsiung S

Classifications

• G06F9/3834 Primary

  Maintaining memory consistency · CPC title

• G06F9/3824

  Operand accessing · CPC title

• G06F9/30043

  LOAD or STORE instructions; Clear instruction · CPC title

• G06F9/34

  Addressing or accessing the instruction operand or the result {; Formation of operand address; Addressing modes (address translation G06F12/00)} · CPC title

• G06F9/355

  Indexed addressing · CPC title