Uniform electrochemical plating of metal onto arrays of pillars having different lateral densities and related technology

Patent metadata

Field	Value
Publication number	US-11527505-B2
Application number	US-202017102253-A
Country	US
Kind code	B2
Filing date	Nov 23, 2020
Priority date	Dec 15, 2016
Publication date	Dec 13, 2022
Grant date	Dec 13, 2022

Abstract

A semiconductor die assembly in accordance with an embodiment of the present technology includes first and second semiconductor dies spaced apart from one another. The first semiconductor die has a major surface with non-overlapping first and second regions. The semiconductor die assembly further includes an array of first pillars extending heightwise from the first region of the major surface of the first semiconductor die toward the second semiconductor die. Similarly, the semiconductor die assembly includes an array of second pillars extending heightwise from the second region of the major surface of the first semiconductor die toward the second semiconductor die. The first and second pillars have different lateral densities and different average widths. The latter difference at least partially offsets an effect of the former difference on relative metal deposition rates of an electrochemical plating process used to form the first and second pillars.

First claim

I claim:

1. A method of forming pillars in a semiconductor die assembly, comprising:
forming a first pattern of first holes and a second pattern of second holes in a material on a semiconductor die; and
depositing a conductive material into the first holes to a first elevation relative to the surface of the material and concurrently depositing the conductive material into the second holes to a second elevation relative to the surface of the material, wherein the first elevation is different than the second elevation;
wherein the conductive material in the first holes defines first pillars having a first height from a major surface of the semiconductor die and the conductive material in the second holes defines second pillars having a second height from the major surface of the semiconductor die, and wherein the first height is different than the second height.

2. The method of claim 1 wherein:
each of the first holes has a first width and each of the second holes has a second width, and the first width is greater than the second width; and
depositing the conductive material comprises concurrently electroplating the conductive material into the first holes and the second holes.

3. The method of claim 1 wherein:
the first holes have a first lateral density and the second holes have a second lateral density, and the first lateral density is greater than the second lateral density; and
depositing the conductive material comprises concurrently electroplating the conductive material into the first holes and the second holes.

4. The method of claim 1 wherein:
the first holes have a first diameter and the second holes have a second diameter, and the first diameter is greater than the second diameter;
each first hole is surrounded by a plurality of second holes; and
depositing the conductive material comprises concurrently electroplating the conductive material into the first holes and the second holes.

5. The method of claim 1 wherein:
the first pillars are electrical-interconnect pillars that are electrically coupled to circuitry components and the second pillars project are dummy pillars electrically isolated from the circuitry; and
a first width of each of the electrical-interconnect pillars is greater than a second width of each of the dummy pillars.

6. The method of claim 1 , further comprising:
forming a third pattern of third holes in the material on the semiconductor die; and
depositing the conductive material into the third holes concurrently with depositing the conductive material into the first holes and the second holes, wherein the conductive material is deposited into the third holes to a third elevation relative to the surface of the material, and the third elevation is different than first elevation and the second elevation.

7. The method of claim 1 wherein the first holes and the second holes are arranged in clusters, with each cluster having a central first hole and a plurality of second holes around the central first hole.

8. The method of claim 1 , further comprising designing the first pattern of first holes to have a first lateral spacing between adjacent first holes and the second patter of second holes to have a second lateral spacing between adjacent second holes, and wherein the first average lateral spacing is greater than the second average lateral spacing.

Assignees

• Micron Technology Inc

Inventors

• Hacker Jonathan S

Classifications

• H10W72/07254

  changes in dispositions · CPC title

• H10W72/07252

  changes in structures or sizes · CPC title

• H10W72/01235

  by plating, e.g. electroless plating or electroplating · CPC title

• H10W72/267

  Multiple bump connectors having different functions · CPC title

• H10W72/265

  Providing thermal transfer, e.g. thermal bumps · CPC title