Level dependent error correction code protection in multi-level non-volatile memory

Patent metadata

Field	Value
Publication number	US-11527300-B2
Application number	US-202117213486-A
Country	US
Kind code	B2
Filing date	Mar 26, 2021
Priority date	Aug 26, 2020
Publication date	Dec 13, 2022
Grant date	Dec 13, 2022

Abstract

A method, apparatus, and system for level dependent error correction code protection in multi-level non-volatile memory. A write command to write data to a non-volatile memory array may be received. At least one multi-level page of multi-level storage cells may be determined for the write data. A coding rate for the write data of the at least one multi-level page may be determined based on an attribute of the at least one multi-level page. An ECC codeword may be generated that satisfies the coding rate and includes the write data. The ECC codeword may then be stored on the at least one multi-level page.

First claim

What is claimed is:

1. A method, comprising:
receiving a write command to write data to a non-volatile memory array;
determining a multi-level page of multi-level storage cells for write data of the write command;
determining a coding rate for write data of at least one multi-level page based on an attribute of the at least one multi-level page, wherein the attribute of the at least one multi-level page comprises a reliability attribute based on a relationship between data integrity among different multi-level pages on a same multi-level storage cell;
generating an ECC codeword that satisfies the coding rate and includes the write data; and
storing the ECC codeword on the at least one multi-level page.

2. The method of claim 1 , wherein the attribute comprises a reliability attribute based on a multi-level storage cell encoding configured to define a plurality of multi-level pages within a page of the non-volatile memory array such that two or more of the plurality of multi-level pages have different reliability attributes.

3. The method of claim 2 , wherein the multi-level storage cell encoding defines one memory state transition for a lower multi-level page, two memory state transitions for a middle multi-level page, six memory state transitions for an upper multi-level page, and six memory state transitions for a top multi-level page.

4. The method of claim 2 , wherein the multi-level storage cell encoding defines one memory state transition for a lower multi-level page, two memory state transitions for a middle multi-level page, four memory state transitions for an upper multi-level page, and eight memory state transitions for a top multi-level page.

5. The method of claim 2 , wherein the multi-level storage cell encoding defines two memory state transitions for a lower multi-level page, three memory state transitions for a middle multi-level page, five memory state transitions for an upper multi-level page, and five memory state transitions for a top multi-level page.

6. The method of claim 1 , wherein the attribute comprises a bit error rate for the at least one multi-level page.

7. The method of claim 1 , wherein the attribute comprises a type of multi-level page and the type comprises one of a lower multi-level page, a middle multi-level page, an upper multi-level page, and a top multi-level page.

8. The method of claim 1 , wherein the attribute comprises a number of read levels defined for the at least one multi-level page by a multi-level storage cell encoding.

9. The method of claim 1 , wherein the attribute comprises a reliability attribute and determining a coding rate for write data of the at least one multi-level page comprises increasing a coding rate for the at least one multi-level page in response to the at least one multi-level page having a greater reliability attribute than other multi-level pages.

10. The method of claim 1 , wherein the ECC codeword comprises a payload and a parity section and wherein determining the coding rate further comprises:
increasing a payload size of the payload in response to the attribute indicating greater data integrity for data stored on the at least one multi-level page relative to data stored on another multi-level page stored on the multi-level storage cells;
decreasing a parity size of the parity section in response to, and by a same amount as, the increased payload size;
decreasing the payload size of the payload in response to the attribute indicating less data integrity for data stored on the at least one multi-level page relative to data stored on another multi-level page stored on the multi-level storage cells;
increasing a parity size of the parity section in response to, and by the same amount as, the decreased payload size; and
wherein the parity size changes in proportion to the payload size such that the ECC codeword maintains a same size.

11. The method of claim 1 , wherein the non-volatile memory array comprises NAND memory cells and the multi-level storage cell encoding is configured to divide up a threshold voltage (Vt) window into a plurality of memory states and assign a binary encoding to each memory state, the binary encoding configured such that each bit in the binary encoding represents a binary value on each multi-level page of a plurality of multi-level pages and wherein the binary encoding is assigned according to a gray code encoding.

12. An apparatus, comprising:
an address allocator configured to determine a multi-level page to store a set of data blocks associated with a set of write commands; and
a packetizer configured to:
combine the set of data blocks into a payload for an ECC codeword;
change a payload size for the payload in response to a reliability attribute of the determined multi-level page satisfying a threshold, wherein the reliability attribute is based on a relationship between data integrity among different multi-level pages on a same multi-level storage cell; and
signal the changed payload size to an error correction code encoder configured to generate the ECC codeword.

13. The apparatus of claim 12 , wherein the packetizer is configured to increase the payload size in response to the reliability attribute identifying the multi-level page as having higher data integrity than another multi-level page configured to be stored on a physical page that is also configured to store the multi-level page.

14. The apparatus of claim 12 , wherein the ECC codeword comprises the payload and a parity section and the error correction code encoder is configured proportionally change the parity section in response to the packetizer changing the payload size such that the ECC codeword remains a same size as ECC codewords for which the packetizer does not change the payload size.

15. The apparatus of claim 12 , wherein each data block comprises a set of data sectors and the packetizer is configured to change the payload size by adding or removing data sectors to a default payload size and the error correction code encoder is configured to proportionally change a parity size by adding or removing redundancy data sized to have the same size as the added or removed data sectors.

16. The apparatus of claim 12 , wherein the packetizer is configured to set a flag to signal the changed payload size to the error correction code encoder.

17. A system, comprising:
a non-volatile memory array comprising Quad-level Cell (QLC) memory cells; and
a storage controller comprising:
a flash translation layer configured to:
convert a logical block address (LBA) of a storage command into a physical block address (PBA) assigned to a multi-level page of QLC memory cells; and
associate write data of a plurality of write commands with the multi-level page, the multi-level page having a type selected from the group consisting of a lower multi-level page, a middle multi-level page, an upper multi-level page, and a top multi-level page;

an error correction code encoder configured to:
generate ECC codewords for the write data assigned to the multi-level page;
adjust an ECC strength for the generated ECC codewords in response to the multi-level page comprising at least one type, wherein the at least one type of the multi-level page provides a relationship between data integrity among different multi-level pages on a same multi-level storage cell; and

a read/write circuit configured to store the ECC codewords on the multi-level page in response to write commands.

18. The system of claim 17 , wherein the lower multi-level page is configured to include a single memory state transition

Assignees

• Western Digital Tech Inc

Inventors

• Yang Nian
• Sharma Sahil
• Singidi Harish

Classifications

• G06F11/1072

  in multilevel memories · CPC title

• G06F11/1048

  using arrangements adapted for a specific error detection or correction feature · CPC title

• G11C29/42 Primary

  using error correcting codes [ECC] or parity check · CPC title

• G11C29/24

  Accessing extra cells, e.g. dummy cells or redundant cells · CPC title

• G06F2212/7201

  Logical to physical mapping or translation of blocks or pages · CPC title