Data storage device and method for storing multiple codewords and redundancy information at a word line

Patent metadata

Field	Value
Publication number	US-9766976-B2
Application number	US-201514733184-A
Country	US
Kind code	B2
Filing date	Jun 8, 2015
Priority date	Jun 8, 2015
Publication date	Sep 19, 2017
Grant date	Sep 19, 2017

Abstract

A method includes generating a first error correcting code (ECC) codeword and a second ECC codeword. The method further includes generating redundancy information based on at least a portion of the first ECC codeword and further based on at least a portion of the second ECC codeword. The method further includes storing the first ECC codeword, the second ECC codeword, and the redundancy information at a word line of a memory of a data storage device.

First claim

What is claimed is:

1. A method comprising:
in a data storage device that includes a memory, performing:
generating a first error correcting code (ECC) codeword and a second ECC codeword; and
based on detecting an indication that a physical page of the memory is to store redundancy information:
adjusting a configuration associated with the physical page from a first scheme that stores user data to a logical page of the physical page to an extended multi-level cell (MLC) scheme that stores the redundancy information to the logical page;
generating the redundancy information based on at least a portion of the first ECC codeword and further based on at least a portion of the second ECC codeword; and
storing the first ECC codeword, the second ECC codeword, and the redundancy information at the physical page.

2. The method of claim 1 , wherein the first ECC codeword corresponds to a first logical page to be stored at the physical page, wherein the logical page corresponds to a second logical page at the physical page, and wherein the second ECC codeword corresponds to a third logical page to be stored at the physical page.

3. The method of claim 2 , wherein the second logical page represents the redundancy information and further represents invalid data, and wherein the first logical page and the second logical page represent valid data.

4. The method of claim 3 , wherein the invalid data includes a sequence of logic one bits.

5. The method of claim 1 , further comprising sensing the physical page to generate a representation of the redundancy information in response to an error rate of one or more of a representation of the first ECC codeword or a representation of the second ECC codeword satisfying a threshold.

6. The method of claim 5 , further comprising error correcting one or more of the representation of the first ECC codeword or the representation of the second ECC codeword using the representation of the redundancy information.

7. The method of claim 1 , wherein the memory has a three-dimensional (3D) memory configuration that is monolithically formed in one or more physical levels of arrays of memory cells, the one or more physical levels of arrays of memory cells having an active area disposed above a silicon substrate, and wherein the data storage device further includes circuitry associated with operation of the memory cells.

8. A data storage device comprising:
a memory die, the memory die including a non-volatile memory; and
a controller coupled to the memory die, wherein the controller is configured to, based on detecting an indication that a particular region of the non-volatile memory is to store redundancy information:
adjust a configuration associated with the particular region from a first technique that stores user data to a logical page of the particular region to an extended multi-level cell (MLC) technique that stores the redundancy information to the logical page;
generate the redundancy information based on at least a subset of first encoded data and further based on at least a subset of second encoded data; and
store the first encoded data, the second encoded data, and the redundancy information at the particular region.

9. The data storage device of claim 8 , wherein the controller includes an error correcting code (ECC) engine configured to generate the first encoded data and the second encoded data.

10. The data storage device of claim 9 , wherein the first encoded data includes a first ECC codeword, and wherein the second encoded data includes a second ECC codeword.

11. The data storage device of claim 9 , wherein the subset of the first encoded data includes a sub-sector of a first ECC codeword, and wherein the subset of the second encoded data includes a sub-sector of a second ECC codeword.

12. The data storage device of claim 8 , wherein the non-volatile memory has a three-dimensional (3D) memory configuration that is monolithically formed in one or more physical levels of arrays of memory cells, the one or more physical levels of arrays of memory cells having an active area above a silicon substrate, and further comprising circuitry associated with operation of the memory cells.

13. An apparatus comprising:
means for storing data; and
means for controlling the means for storing data, the means for controlling configured to, based on detecting an indication that a physical page of the means for storing data is to store redundancy information:
adjust a configuration associated with the physical page from a first scheme that stores user data to a logical page of the physical page to an extended multi-level cell (MLC) scheme that stores the redundancy information to the logical page;
generate the redundancy information based on a first error correcting code (ECC) codeword and a second ECC codeword; and
send the first ECC codeword, the second ECC codeword, and the redundancy information to the means for storing data to be stored at the physical page.

14. The apparatus of claim 13 , wherein the first ECC codeword corresponds to a lower page of the physical page, wherein the second ECC codeword corresponds to an upper page of the physical page, and wherein the logical page corresponds to a middle page of the physical page.

15. The apparatus of claim 14 , wherein the middle page represents the redundancy information and further represents invalid data, and wherein the upper page and the lower page represent valid data.

16. The apparatus of claim 15 , wherein the invalid data includes a sequence of logic one bits.

17. The apparatus of claim 13 , wherein the means for storing data has a three-dimensional (3D) memory configuration that is monolithically formed in one or more physical levels of arrays of memory cells, the one or more physical levels of arrays of memory cells having an active area above a silicon substrate, and further comprising circuitry associated with operation of the memory cells.

18. The method of claim 1 , wherein the indication corresponds to one or more of a health level associated with the physical page, a location of the physical page in a memory die of the data storage device, or a number of program/erase cycles associated with the physical page.

19. The method of claim 1 , further comprising:
in response to detecting the indication, adjusting an entry of a table of the data storage device from indicating the first scheme to indicating the extended MLC scheme.

20. The method of claim 19 , wherein the table further indicates that a second storage region of the data storage device is associated with the first scheme, and wherein the extended MLC scheme is applied to the physical page independently of the second storage region.

Assignees

• Sandisk Technologies Inc
• Sandisk Technologies Llc

Inventors

• D'Abreu Manuel Antonio
• Li Zongwang

Classifications

• G11C29/52

  Protection of memory contents; Detection of errors in memory contents · CPC title

• H03M13/2942

  wherein a block of parity bits is computed only from combined information bits or only from parity bits, e.g. a second block of parity bits is computed from a first block of parity bits obtained by systematic encoding of a block of information bits, or a block of parity bits is obtained by an XOR combination of sub-blocks of information bits · CPC title

• H03M13/2906

  using block codes (H03M13/2957 takes precedence) · CPC title

• G06F11/1072 Primary

  in multilevel memories · CPC title

• G11C2029/0411

  Online error correction · CPC title