Enhancing the effectiveness of read scan performance and reliability for non-volatile memory

Patent metadata

Field	Value
Publication number	US-10896123-B2
Application number	US-201816218800-A
Country	US
Kind code	B2
Filing date	Dec 13, 2018
Priority date	Dec 13, 2018
Publication date	Jan 19, 2021
Grant date	Jan 19, 2021

Abstract

Techniques are described for performing a read scan process on a non-volatile memory system in order to determine memory blocks that may have a high bit error rate, where if such blocks are found they can be refreshed. Rather than work through the blocks of a memory system sequentially based on the physical block addresses, the memory system maintains a measure of data quality, such as an estimated or average bit error rate, for multi-block groups. For example, the groups can correspond to regions of memory die in the system. The groups are ranked by their data quality, with the groups being scanned in order of the data quality. The blocks within a group can also be ranked, based on factors such as the program/erase count.

First claim

What is claimed is:

1. An apparatus, comprising:
a non-volatile memory comprising a plurality of blocks formed on one or more memory die, each block having a plurality of non-volatile memory cells; and
one or more control circuits configured to:
maintain, for each of a plurality of sets of blocks, an estimate of bit error rate for the set of blocks as a whole, where each set of blocks corresponds to a physically adjacent plurality of blocks on one of the memory die and includes a plurality of blocks, each of the blocks belonging to one of the sets of blocks;
establish an order for the sets of blocks based on the estimates of bit error rate; and
scan one or more of the sets of blocks according to the order, including:
ordering the individual blocks within a set to be scanned; and
individually scanning the individual blocks of the set of blocks being scanned according to the ordering of the individual blocks within the set to be scanned; and
determine a corresponding amount of error for each of the individual blocks of the set of blocks being scanned.

2. The apparatus of claim 1 , wherein the one or more control circuits are further configured to compare the corresponding amount of error for the individual blocks against a threshold value and, in response to the amount of error exceeding threshold value, refreshing the corresponding block.

3. The apparatus of claim 1 , wherein the one or more control circuits are configured to order the individual blocks within the set to be scanned based on a program/erase count of each of the individual blocks.

4. The apparatus of claim 1 , wherein the one or more control circuits are configured to order the individual blocks within the set to be scanned based on operating conditions of the apparatus.

5. The apparatus of claim 1 , wherein each of the blocks include a plurality of word lines, each word line storing a plurality of ECC codewords, and the one or more control circuits are further configured to scan the individual blocks by reading and decoding a single ECC codeword from a scanned word line.

6. The apparatus of claim 1 , wherein each of the blocks is configured to store a plurality of pages of data, a page of data including a plurality of ECC codewords, and the one or more control circuits are further configured to scan the individual blocks by reading and decoding a single ECC codeword from a scanned page of data.

7. The apparatus of claim 1 , wherein the non-volatile memory comprises a monolithic three-dimensional semiconductor memory device where the non-volatile memory cells are arranged in multiple physical levels above a substrate and comprise a charge storage medium.

8. A method, comprising:
maintaining, for each of a plurality of groups of blocks of a non-volatile memory, corresponding metadata including an estimated bit error rate for the group of blocks, each of the groups of blocks including a distinct plurality of physically adjacent blocks on a memory die;
ranking the groups of blocks according to the corresponding estimated bit error rate; and
scanning one of more of the groups of blocks in an order based on the ranking, the scanning of a group including:
for each block of the group, reading a portion of data stored in the block;
determining an error rate for each block of the group of blocks based on the reading of the portion of the data stored in the block;
determining an ordering of the blocks within a group to be scanned; and
scanning the blocks within the group according to the ordering of the blocks within the group to be scanned.

9. The method of claim 8 , wherein the ordering of the blocks within the group to be scanned is based on program/erase counts of the blocks within the group.

10. The method of claim 8 , further comprising:
comparing the determined error rate for each of the blocks to a threshold; and
in response to the error rate of a block exceeding the threshold:
reading out data of the block;
correcting the read out data of the block; and
rewriting the corrected data to the non-volatile memory.

11. The method of claim 8 , wherein each of the blocks stores a plurality of pages of data, each of the pages including multiple ECC codewords, and the reading the portion of the data stored in the block includes:
reading out and decoding an ECC codeword word for each page of the block.

12. The method of claim 8 , wherein the reading of the portion of data stored in the block includes reading one or more ECC codewords from the block, and determining an error rate includes decoding of the ECC codewords.

13. A non-volatile memory system comprising:
one or more memory die, each having a plurality of blocks of non-volatile memory cells; and
a controller for the non-volatile memory system, the controller configured to maintain a data quality level indication for each of a plurality of regions of the one or more memory die, each of the regions including a plurality of physically adjacent blocks on one of the memory die, and each of the blocks belonging to one of the regions, the controller further configured to determine a region ordering for the regions based on the quality level indications, to select a region based on the region ordering, to determine an error estimation for data of each of the blocks of the selected region, to determine a block ordering for the blocks of selected region, and to determine the error estimation for data of each of the blocks of the selected region according to the block ordering.

14. The non-volatile memory system of claim 13 , where in the block ordering is based on program/erase counts of the blocks within the selected region.

15. The non-volatile memory system of claim 14 , wherein, in response to the error estimation for data of a block exceeding a threshold, the controller is further configured to perform a refresh operation on the block for which the error estimation for the data exceeds the threshold.

16. The non-volatile memory system of claim 15 , wherein the refresh operation includes reading out data of the block for which the error estimation for the data exceeds the threshold, correcting the read out data, and writing the corrected data to a different block.

Assignees

• Western Digital Tech Inc

Inventors

• Yang Nian Niles
• Sharma Sahil
• Reusswig Philip
• Sehgal Rohit

Classifications

• G11C16/3418

  Disturbance prevention or evaluation; Refreshing of disturbed memory data · CPC title

• G06F12/0246 Primary

  in block erasable memory, e.g. flash memory · CPC title

• G11C16/3431

  Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step · CPC title

• G11C29/52 Primary

  Protection of memory contents; Detection of errors in memory contents · CPC title

• G06F11/1072

  in multilevel memories · CPC title