Vertical fin field effect transistor with a reduced gate-to-bottom source/drain parasitic capacitance

Patent metadata

Field	Value
Publication number	US-11515401-B2
Application number	US-201916685022-A
Country	US
Kind code	B2
Filing date	Nov 15, 2019
Priority date	Dec 21, 2017
Publication date	Nov 29, 2022
Grant date	Nov 29, 2022

Abstract

A method of forming a vertical fin field effect device is provided. The method includes, forming a vertical fin on a substrate, forming a masking block on the vertical fin, wherein the masking block extends a distance outward from the vertical fin sidewalls and endwalls, and a portion of the substrate surrounding the masking block is exposed. The method further includes removing at least a portion of the exposed portion of the substrate to form a recess and a fin mesa below the vertical fin, removing a portion of the fin mesa to form an undercut recess below an overhanging portion of the masking block, forming a spacer layer on the masking block and in the undercut recess, and removing a portion of the spacer layer to form an undercut spacer in the undercut recess.

First claim

What is claimed is:

1. A method of forming a vertical fin field effect device, comprising:
forming a masking block on a vertical fin, wherein the masking block extends asymmetrically outward from the vertical fin sidewalls and endwalls, and a portion of the substrate surrounding the masking block is exposed;
removing at least a portion of the exposed portion of the substrate to form a recess and a fin mesa below the masking block and the vertical fin;
removing a portion of the fin mesa from beneath the masking block to form an undercut recess below an overhanging portion of the masking block;
forming a spacer layer on the masking block and in the undercut recess; and
removing a portion of the spacer layer to form an undercut spacer in the undercut recess beneath the masking block.

2. The method of claim 1 , further comprising forming a fill layer in the recess, and reducing the height of the fill layer to form an isolation plug.

3. The method of claim 2 , further comprising forming a bottom spacer on the exposed top surface of the fin mesa and undercut spacer, and on the exposed top surface of the isolation plug, wherein the top surface of the undercut spacer is flush with the top surface of the fin mesa.

4. The method of claim 3 , further comprising forming a gate dielectric layer on the bottom spacer, sidewalls of the undercut spacer, and the vertical fin.

5. The method of claim 4 , wherein the undercut recess is formed to a depth in a range of about 3 nm to about 15 nm.

6. The method of claim 5 , wherein the masking block extends different distances from each of the vertical fin endwalls.

7. The method of claim 6 , wherein the masking block extends a distance in a range of about 6 nm to about 12 nm from one vertical fin endwall, and a distance in a range of about 12 nm to about 36 nm from the opposite vertical fin endwall.

8. The method of claim 7 , wherein the material of the undercut spacer is selected from the group consisting of silicon nitride (SiN), a silicon oxynitride (SiON), a silicon carbonitride (SiCN), a silicon boronitride (SiBN), a silicon borocarbide (SiBC), a silicon boro carbonitride (SiBCN), and combinations thereof.

9. The method of claim 8 , wherein the spacer layer is formed by a conformal deposition, and the bottom spacer is formed by a directional deposition.

10. A method of forming a pair of vertical fin field effect devices, comprising:
forming two vertical fins on a substrate;
forming a masking block on each of the two vertical fins, wherein the masking block extends a distance outward from the sidewalls and endwalls of each vertical fin, wherein a portion of the substrate surrounding each of the two masking blocks and between the two masking blocks is exposed;
removing the exposed portion of the substrate to forma recess surrounding each of the masking blocks, and a fin mesa below each of the vertical fins;
removing a portion of each of the fin mesas to form an undercut recess below an overhanging portion of each of the masking blocks;
forming a spacer layer on each of the masking blocks and in each of the undercut recess; and
removing the spacer layer on the masking blocks to form an undercut spacer in each of the undercut recess.

11. The method of claim 10 , wherein the undercut recess is formed to a depth in a range of about 3 nm to about 15 nm.

12. The method of claim 11 , wherein the two vertical fins are separated by a fin pitch in a range of about 30 nm to about 100 nm.

13. The method of claim 12 , wherein two facing sidewalls of the two undercut spacers are separated by a distance in the range of about 6 nm to about 20 nm.

14. The method of claim 13 , further comprising forming a fill layer in the recess, and reducing the height of the fill layer to form an isolation plug, wherein the height of the isolation plug is less than the height of the two undercut spacers.

15. A method of forming a pair of vertical fin field effect devices, comprising:
forming a first masking block on a first vertical fin, wherein the masking block extends asymmetrically outward from the first vertical fin sidewalls and endwalls, and a portion of the substrate surrounding the first masking block is exposed;
forming a second masking block on a second vertical fin adjacent to the first vertical fin, wherein the second masking block extends asymmetrically outward from the second vertical fin sidewalls and endwalls, and a portion of the substrate surrounding the second masking block and between the second masking block and the first masking block is exposed;
removing at least a portion of the exposed portion of the substrate to form a recess and a fin mesa below the vertical fin;
removing a portion of the first fin mesa to form a first undercut recess below an overhanging portion of the first masking block and a portion of the second fin mesa to form a second undercut recess below an overhanging portion of the second masking block;
forming a spacer layer on the first masking block and in the first undercut recess and on the second masking block and in the second undercut recess; and
removing a portion of the spacer layer to form a first undercut spacer in the first undercut recess and a second undercut spacer in the second undercut recess.

16. The method of claim 15 , wherein the first asymmetrical masking block extends a distance in a range of about 6 nm to about 12 nm from one vertical fin endwall, and a distance in a range of about 12 nm to about 36 nm from the opposite vertical fin endwall.

17. The method of claim 16 , further comprising forming a fill layer in the recess, and reducing the height of the fill layer to form an isolation plug, wherein the height of the isolation plug is less than the height of the first and second undercut spacers.

18. The method of claim 16 , further comprising forming a bottom spacer on the top surface of the first fin mesa, first undercut spacer, second fin mesa, second undercut spacer, and isolation plug.

19. The method of claim 18 , further comprising forming a gate dielectric layer on the bottom spacer, sidewalls of the first and second undercut spacers, and sidewalls and endwalls of the first and second vertical fins.

20. The method of claim 19 , further comprising a work function layer and a conductive gate fill on the gate dielectric layer.

Assignees

• IBM

Inventors

• Zhang Chen
• Cheng Kangguo
• Miao Xin
• Xu Wenyu

Classifications

• H01L29/78642

  Electricity · mapped topic

• H01L29/1033

  Electricity · mapped topic

• H01L29/66666

  Electricity · mapped topic

• H01L29/66742

  Electricity · mapped topic

• H01L29/78684

  Electricity · mapped topic