Fin field effect transistor (finFET) device including a set of merged fins formed adjacent a set of unmerged fins

Patent metadata

Field	Value
Publication number	US-9472572-B2
Application number	US-201414270833-A
Country	US
Kind code	B2
Filing date	May 6, 2014
Priority date	May 6, 2014
Publication date	Oct 18, 2016
Grant date	Oct 18, 2016

Abstract

Approaches for simultaneously providing a set of merged and unmerged fins in a fin field effect transistor device (FinFET) are disclosed. In at least one approach, the FinFET device includes: a set of merged fins and a set of unmerged fins formed from a substrate, the set of unmerged fins adjacent the set of merged fins; and a planar block formed from the substrate, the planar block adjacent one of: the set of merged fins, and the set of unmerged fins. The FinFET device further includes an epitaxial material over each of the set of merged fins and each of the set of unmerged fins, wherein the epitaxial material merges together over the set of merged fins and remains unmerged over the set of unmerged fins. In at least one approach, the set of merged fins and the set of unmerged fins is formed using a sidewall image transfer process.

First claim

What is claimed is:

1. A method for forming a fin field effect transistor (FinFET) device, comprising:
forming a set of merged fins from a substrate;
forming a set of unmerged fins from the substrate, the set of unmerged fins adjacent the set of merged fins; and
forming a planar block from the substrate, the planar block adjacent one of: the set of merged fins, and the set of unmerged fins;
wherein forming the set of merged fins, forming the set of unmerged fins, and forming the planar block comprise:
forming a first hardmask over the substrate;
patterning a plurality of merged fin structures and a planar block structure over the first hardmask;
forming a second hard mask over the plurality of merged fin structures and the planar block structure; and
depositing a third hardmask over the second hardmask.

2. The method according to claim 1 , wherein the set of merged fins and the set of unmerged fins are formed using a sidewall image transfer process.

3. The method according to claim 1 , the first hardmask, the second hardmask, and the third hardmask comprising one of: silicon, and silicon nitride.

4. The method according to claim 1 , further comprising:
forming a set of spacers over the third hardmask; and
recessing the substrate that remains uncovered by the set of spacers to form the set of merged fins and the set of unmerged fins.

5. The method according to claim 1 , wherein the set of spacers is formed over the set of merged fin structures and over an unmerged region of the FinFET device, the unmerged region of the FinFET device adjacent the set of merged fin structures.

6. The method according to claim 1 , further comprising growing an epitaxial material over each of the set of merged fins and each of the set of unmerged fins, wherein the epitaxial material merges together over the set of merged fins, and wherein the epitaxial material remains unmerged over the set of unmerged fins.

7. The method according to claim 1 , further comprising providing a shallow trench isolation (STI) material between each of the set of unmerged fins and each of the set of merged fins.

8. A method for forming a fin field effect transistor (FinFET) device, comprising:
forming a set of merged fins from a substrate;
forming a set of unmerged fins from the substrate, the set of unmerged fins adjacent the set of merged fins; and
forming a planar block from the substrate, the planar block adjacent forming a planar block from the substrate, the planar block adjacent the set of unmerged fins;
wherein forming the set of merged fins, forming the set of unmerged fins, and forming the planar block comprise:
forming a first hardmask over the substrate;
patterning a plurality of merged fin structures and a planar block structure over the first hardmask;
forming a second hard mask over the plurality of merged fin structures and the planar block structure; and
depositing a third hardmask over the second hardmask.

9. The method according to claim 8 , wherein the set of merged fins and the set of unmerged fins are formed using a sidewall image transfer process.

10. The method according to claim 8 , the first hardmask, the second hardmask, and the third hardmask comprising one of: silicon, and silicon nitride.

11. The method according to claim 8 , further comprising growing an epitaxial material over each of the set of merged fins and each of the set of unmerged fins, wherein the epitaxial material merges together over the set of merged fins, and wherein the epitaxial material remains unmerged over the set of unmerged fins.

12. The method according to claim 8 , further comprising providing a shallow trench isolation (STI) material between each of the set of unmerged fins and each of the set of merged fins.

13. The method according to claim 8 , further comprising:
forming a set of spacers over the third hardmask; and
recessing the substrate that remains uncovered by the set of spacers to form the set of merged fins and the set of unmerged fins.

14. The method according to claim 13 , wherein the set of spacers is formed over the set of merged fin structures and over an unmerged region of the FinFET device, the unmerged region of the FinFET device adjacent the set of merged fin structures.

Assignees

• Globalfoundries Inc

Inventors

• Zang Hui

Classifications

• H10D62/822

  comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions · CPC title

• H10D86/011

  comprising FinFETs · CPC title

• H10D84/853

  comprising FinFETs · CPC title

• H10D84/834

  comprising FinFETs · CPC title

• H10D84/0193

  the components including FinFETs · CPC title