Gate-all-around integrated circuit structures having underlying dopant-diffusion blocking layers

Patent metadata

Field	Value
Publication number	US-11469299-B2
Application number	US-201816146785-A
Country	US
Kind code	B2
Filing date	Sep 28, 2018
Priority date	Sep 28, 2018
Publication date	Oct 11, 2022
Grant date	Oct 11, 2022

Abstract

Gate-all-around integrated circuit structures having underlying dopant-diffusion blocking layers are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires above a fin. The fin includes a dopant diffusion blocking layer on a first semiconductor layer, and a second semiconductor layer on the dopant diffusion blocking layer. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires. A second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal nanowires.

First claim

What is claimed is:

1. An integrated circuit structure, comprising:
a vertical arrangement of horizontal nanowires above a fin, the fin comprising a dopant diffusion blocking layer on a first semiconductor layer, and a second semiconductor layer on the dopant diffusion blocking layer;
a gate stack around the vertical arrangement of horizontal nanowires, wherein a portion of the gate stack is vertically between a bottommost one of the vertical arrangement of horizontal nanowires and the second semiconductor layer;
a first epitaxial source or drain structure at a first end of the vertical arrangement of horizontal nanowires; and
a second epitaxial source or drain structure at a second end of the vertical arrangement of horizontal nanowires.

2. The integrated circuit structure of claim 1 , wherein the fin comprises a portion of a bulk silicon substrate, and wherein the first semiconductor layer is a region within the portion of the bulk silicon substrate.

3. The integrated circuit structure of claim 1 , wherein the first and second epitaxial source or drain structures are on the second semiconductor layer.

4. The integrated circuit structure of claim 1 , wherein the first and second epitaxial source or drain structures are on a recessed portion of the second semiconductor layer.

5. The integrated circuit structure of claim 1 , wherein the first and second epitaxial source or drain structures are on a portion of the dopant diffusion blocking layer.

6. The integrated circuit structure of claim 1 , wherein the dopant diffusion blocking layer comprises carbon and silicon.

7. The integrated circuit structure of claim 1 , wherein the dopant diffusion blocking layer further comprises germanium.

8. The integrated circuit structure of claim 1 , wherein the first and second epitaxial source or drain structures are non-discrete first and second epitaxial source or drain structures.

9. The integrated circuit structure of claim 1 , wherein the first and second epitaxial source or drain structures are discrete first and second epitaxial source or drain structures.

10. The integrated circuit structure of claim 1 , wherein the vertical arrangement of horizontal nanowires is a vertical arrangement of silicon nanowires, a vertical arrangement of silicon germanium nanowires, a vertical arrangement of germanium nanowires, or a vertical arrangement of Group III-V material nanowires .

11. The integrated circuit structure of claim 1 , wherein the gate stack comprises a high-k gate dielectric layer and a metal gate electrode.

12. An integrated circuit structure, comprising:
a vertical arrangement of horizontal nanowires above a fin, the fin comprising a carbon-containing layer on an N-type semiconductor layer, and a semiconductor layer on the carbon-containing layer;
a gate stack around the vertical arrangement of horizontal nanowires, wherein a portion of the gate stack is vertically between a bottommost one of the vertical arrangement of horizontal nanowires and the semiconductor layer;
a first P-type epitaxial source or drain structure at a first end of the vertical arrangement of horizontal nanowires; and
a second P-type epitaxial source or drain structure at a second end of the vertical arrangement of horizontal nanowires.

13. The integrated circuit structure of claim 12 , wherein the fin comprises a portion of a bulk silicon substrate, and wherein the N-type semiconductor layer is a region within the portion of the bulk silicon substrate.

14. The integrated circuit structure of claim 12 , wherein the first and second P-type epitaxial source or drain structures are on the semiconductor layer.

15. The integrated circuit structure of claim 12 , wherein the first and second P-type epitaxial source or drain structures are on a recessed portion of the semiconductor layer.

16. The integrated circuit structure of claim 12 , wherein the first and second P-type epitaxial source or drain structures are on a portion of the carbon-containing layer.

17. The integrated circuit structure of claim 12 , wherein the carbon-containing layer further comprises silicon, germanium, or both silicon and germanium.

18. The integrated circuit structure of claim 12 , wherein the first and second P-type epitaxial source or drain structures are non-discrete first and second epitaxial source or drain structures.

19. An integrated circuit structure, comprising:
a vertical arrangement of horizontal nanowires above a fin, the fin comprising a carbon-containing layer on a P-type semiconductor layer, and a semiconductor layer on the carbon-containing layer;
a gate stack around the vertical arrangement of horizontal nanowires, wherein a portion of the gate stack is vertically between a bottommost one of the vertical arrangement of horizontal nanowires and the semiconductor layer;
a first N-type epitaxial source or drain structure at a first end of the vertical arrangement of horizontal nanowires; and
a second N-type epitaxial source or drain structure at a second end of the vertical arrangement of horizontal nanowires.

20. The integrated circuit structure of claim 19 , wherein the fin comprises a portion of a bulk silicon substrate, and wherein the P-type semiconductor layer is a region within the portion of the bulk silicon substrate.

21. The integrated circuit structure of claim 19 , wherein the first and second N-type epitaxial source or drain structures are on the semiconductor layer.

22. The integrated circuit structure of claim 19 , wherein the first and second N-type epitaxial source or drain structures are on a recessed portion of the semiconductor layer.

23. The integrated circuit structure of claim 19 , wherein the first and second N-type epitaxial source or drain structures are on a portion of the carbon-containing layer.

24. The integrated circuit structure of claim 19 , wherein the carbon-containing layer further comprises silicon, germanium, or both silicon and germanium.

25. The integrated circuit structure of claim 19 , wherein the first and second N-type epitaxial source or drain structures are non-discrete first and second epitaxial source or drain structures.

Assignees

• Intel Corp

Inventors

• Glass Glenn
• Murthy Anand
• Guha Biswajeet
• Crum Dax
• Keys Patrick
• Ghani Tahir
• Ghose Susmita
• Cook Jr Ted

Classifications

• H10P76/2043

  using an anti-reflective coating · CPC title

• H10P72/7426

  used as a support during build up manufacturing of active devices · CPC title

• H10P72/744

  Details of chemical or physical process used for separating the auxiliary support from a device or a wafer · CPC title

• H10P72/74

  using temporarily an auxiliary support · CPC title

• H10P52/402

  of semiconductor materials · CPC title